Article Details

ID: 1974
Case Type: faq
Category: Device Programming
Related To: ispVM Embedded
Family: LatticeXP2

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Why are padding bits required for every LatticeXP2 FPGA except the LatticeXP2-40 when it is programmed in Slave SPI mode?

The LatticeXP2 configuration memory is arranged in an array. The array size varies depending on the number of logic elements available in the FPGA. The LatticeXP2 array dimensions are as follows:



  • LatticeXP2-5: 1938 rows, each 638 bits wide

  • LatticeXP2-8: 2532 rows, each 772 bits wide

  • LatticeXP2-17: 1658 rows, each 2188 bits wide

  • LatticeXP2-30: 2252 rows, each 2644 bits wide

  • LatticeXP2-40: 2545 rows, each 3384 bits wide

The SPI memory controllers usually require data to be transmitted in multiples of 8-bits.  Therefore a certain amount of padding must be provided so that the SPI memory controller can transmit the data so that it aligns to the requirements of the LatticeXP2 device. Thus a SPI memory controller that sends 8-bits per transaction to a LatticeXP2-8 must break the 772 bit wide data into 8-bit chunks. The 772 bits is not evenly divisible by 8, so 4 additional padding bits must be provided to the SPI memory controller to align the data transmitted to the LatticeXP2-8 correctly.


The LatticeXP2_SSPI.pdf file provided in the documents section of the Lattice ispVM System Software describes the Slave SPI programming process in more detail.