Article Details

ID: 1558
Case Type: faq
Category: Architecture
Related To: IO
Family: LatticeECP3

Search Answer Database

Search Text Image

Are all IOs of LatticeECP3 in high-impedance state when VCC, VCCIO and other power supplies do not have power applied?

The left and right bank IOs on the LatticeECP3 have electrostatic discharge (ESD) protection diodes connected to VCCIO. They are respectively identified with "PL" and "PR" prefixes in their pin name. When the VCCIO pins do not have power applied, the left/right bank IO pins will be at 0.7V - 1.0V because of the ESD diodes are connected to the VCCIO power rail.

All general purpose I/O on the top banks (banks 1 and 8, identified with "PT" prefix in pin name) and some general purpose I/O in banks 3 and 6 on the bottom are high impedance during power up as circuitry provides hot-socket control. The hot-socketable IO in bank 3 and 6 can be identified with the "PB" prefix in their pin name.