The "synthesis LOC" meta comment should work in Verilog unless there is a syntax error in the code. The correct syntax is the following:
reg SamplePhase_90 /* synthesis COMP= SamplePhase_90 LOC="R2C14B" */;
A common mistake is to leave out the COMP constraint while using "synthesis LOC" comment. Refer to the Locating a Block to a Device Site section in FPGA Design Guide, which is available within the ispLEVER files or at http://www.latticesemi.com/view_document?document_id=9762
Alternatively you can specify where a register will be located by using the \u201CLOCATE\u201D command in the logical preference file (.LPF) instead of the \u201Csynthesis LOC\u201D meta comment in the Verilog source.
The following lines in the .LPF file pack the registers into slices:
- LOCATE COMP "DESIGN/SamplePhase_90" SITE "R2C14B";
- LOCATE COMP "DESIGN/SamplePhase_180" SITE "R3C14C";
Note: The location designation R2C14B used in this example refers to the slice located in Row 2, Column 14, Slice B. There are four slices per location and these are labeled A, B, C, or D.