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  • I2C to APB Bridge Reference Design

    Reference Design

    I2C to APB Bridge Reference Design

    With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.
    MachXO2, MachXO3, MachXO3D 
    I2C, APB, AMBA, AHB 
    I2C to APB Bridge Reference Design
  • USB 2.0 Device with FIFO Interface (USB20HF)

    IP Core

    USB 2.0 Device with FIFO Interface (USB20HF)

    USB20HF IP Core provides FIFO & ULPI interface. It supports High Speed and Full Speed functionality for 15 IN/OUT endpoints.
    CrossLink-NX, iCE40 UltraPlus, MachXO2 
    FMC, Data Communication, Camera, ULPI, USB2, FIFO 
    USB 2.0 Device with FIFO Interface (USB20HF)
  • 8N1 UART Transceiver Reference Design

    Reference Design

    8N1 UART Transceiver Reference Design

    8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU
    iCE40 UltraPlus, MachXO2 
    UART, Bus Controllers, TOR Switch 
    8N1 UART Transceiver Reference Design
  • Generic Soft SPI Master Controller Reference Design

    Reference Design

    Generic Soft SPI Master Controller Reference Design

    Provides an interface between a generic processor with parallel bus interface and external SPI devices.
    MachXO2, MachXO3, LatticeECP3, ECP5 / ECP5-5G, CrossLink, CrossLink-NX, iCE40 UltraPlus 
    SPI, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 
    Generic Soft SPI Master Controller Reference Design
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    The RISC-V SM CPU IP processes data and instructions while considering the external interrupts. The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    Certus-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2, Avant-E 
    AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive 
    RISC-V SM CPU IP Core
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3, Mach-NX 
    5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 
    Soft I2C Bus Master
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3 
    5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 
    Soft I2C Slave Peripheral
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, Platform Manager, ECP5 / ECP5-5G, MachXO3 
    Bus Controllers, I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    MachXO, MachXO2, LatticeXP2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 
    I2C, Wishbone, Bus Controllers, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 
    I2C Master - WISHBONE Compatible
  • I3C-S-MIPI-I3C-Basic-Slave-Controller

    IP Core

    I3C-S-MIPI-I3C-Basic-Slave-Controller

    Highly featured, SDR-Capable and HDR-Tolerant Slave controller. Supports hot-join, in-band interrupts, & dynamic addressing. Works to any Lattice FPGA device.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    I3C, MIPI 
    I3C-S-MIPI-I3C-Basic-Slave-Controller
  • JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    Scalable, ultra-high throughput 8/12-bit JPEG decoder. Ideal for low-latency motion-Jpeg streaming. Full-HD or Ultra-HD capable depending on the device.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Data Compression, JPEG, JPEG CODEC 
    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder
  • JPEG-DX-S - Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-S - Baseline and Extended JPEG Decoder

    Compact, 8bit and 12bit per color, JPEG decoder. Ideal for low-latency motion-Jpeg streaming.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Data Compression, JPEG, JPEG CODEC 
    JPEG-DX-S - Baseline and Extended JPEG Decoder
  • JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    Scalable, ultra-high throughput 8/12-bit encoder. Highly configurable with advanced bit-rate control. Ideal for low-latency motion-Jpeg streaming.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Data Compression, JPEG, JPEG CODEC 
    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder
  • JPEG-EX-S - Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-S - Baseline and Extended JPEG Encoder

    Compact, 8bit and 12bit per color, JPEG encoder. Highly configurable with advanced bit-rate control features. Ideal for low-latency motion-Jpeg streaming.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Data Compression, JPEG, JPEG CODEC 
    JPEG-EX-S - Baseline and Extended JPEG Encoder
  • SPMI-CTRL - MIPI SPMI Master or Slave Controller

    IP Core

    SPMI-CTRL - MIPI SPMI Master or Slave Controller

    Highly featured, easy-to-use master or slave controller supporting the latest version of the MIPI-SPMI specification. Portable to any Lattice FPGA device
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Power Management Bus, Power Management, MIPI, SPMI 
    SPMI-CTRL - MIPI SPMI Master or Slave Controller
  • TSN-EP – TSN Ethernet Endpoint Controller

    IP Core

    TSN-EP – TSN Ethernet Endpoint Controller

    Highly flexible core supports timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, Qbv) and frame-preemption (IEEE 802.1Qbu, & 802.3br).
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    IEEE1588, Ethernet, IEEE 802.3, Automotive, Functional Safety, TSN 
    TSN-EP – TSN Ethernet Endpoint Controller
  • UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    IP Core

    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    Standalone, processor-less operation with up to 32 Rx and 32 Tx channels. Supports DHCP, IGMP, ICMP, ARP with cache, Jumbo and super Jumbo IPv4 frames.
    MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 
    Ethernet, IEEE 802.3, JPEG, Video Tx/Rx 
    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack
  • Simple Sigma-Delta ADC

    Reference Design

    Simple Sigma-Delta ADC

    Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
    MachXO, MachXO2, LatticeXP2, iCE40 UltraPlus 
    ADC/DAC, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems 
    Simple Sigma-Delta ADC
  • SPI Slave to PWM Generation

    Reference Design

    SPI Slave to PWM Generation

    Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
    MachXO2, iCE40 UltraPlus 
    SPI, PWM, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Space 
    SPI Slave to PWM Generation
  • MachXO2 I2C Embedded Programming Access Firmware

    Reference Design

    MachXO2 I2C Embedded Programming Access Firmware

    Provides C code for interfacing to MachXO2 from a microcontroller, and RTL for implementing I2C between an external master and the MachXO2
    MachXO2 
    I2C, Soft Processor 
    MachXO2 I2C Embedded Programming Access Firmware
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