Lattice Solutions

IP Core

FFT Compiler IP Core

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X 

Data Communication, DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

IP Core

FIR Filter Generator IP Core

This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.

ECP5 / ECP5-5G, LatticeECP3, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X 

DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

IP Core

​​JESD204B IP Core​

​​The Lattice JESD204B IP Core is a high-speed serial interface used between data converters, and the FPGA device to replace traditional interfaces.​

ECP5 / ECP5-5G, LatticeECP3, CertusPro-NX 

ADC/DAC, DSP, SDR 

IP Core

PCI Express x1, x4 Root Complex Lite IP Core

Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M 

PCIe, Guidance Systems, Automotive, PCIe Bundle, SDR 

IP Core

Timer/Counter IP Core

The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.

Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 LP/HX, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2, MachXO3, MachXO3D, MachXO5-NX 

AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

IP Core

Helion IONOS Image Signal Processing IP Portfolio

Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.

MachXO, LatticeXP2, LatticeECP3, CrossLink, ECP5 / ECP5-5G, CrossLink-NX 

HDR, Image Processing, Video Tx/Rx, Lattice mVision, Automotive 

IP Core

Tri-Speed Ethernet MAC IP Core

The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, LatticeSC/M, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X 

Data Communication, Ethernet, Defense, Automotive, APB, AXI, AXI-Lite Interface, AHB, Ethernet Bundle 

Reference Design

Generic Soft SPI Master Controller Reference Design

Provides an interface between a generic processor with parallel bus interface and external SPI devices.

MachXO2, MachXO3, LatticeECP3, ECP5 / ECP5-5G, CrossLink, CrossLink-NX, iCE40 UltraPlus 

SPI, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3, Mach-NX 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

I2C Bus Master

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device

MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, Platform Manager, ECP5 / ECP5-5G, MachXO3 

Bus Controllers, I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

I2C Master - WISHBONE Compatible

Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus

MachXO, MachXO2, LatticeXP2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 

I2C, Wishbone, Bus Controllers, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

IP Core

DDR3 PHY

Connects a DDR3 memory Controller (MC) to a DDR3 memory device (JESD79-3). Contains all the logic required for functions dependent on FPGA DDR IO primitives

ECP5 / ECP5-5G, LatticeECP3, CrossLink-NX, Certus-NX, CertusPro-NX 

DDR SDRAM, Automotive, Memory Controller Bundle 

IP Core

DDR3 SDRAM Controller

General-purpose complete memory controller interfaces with industry standard DDR3 memory (JESD79-3 Standard), and provides a generic command interface

LatticeECP3, ECP5 / ECP5-5G, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

DDR SDRAM, Automotive, Memory Controller Bundle 

IP Core

Color Space Converter (CSC) IP Core

The Lattice Color Space Converter IP Core is widely parameterizable and can support any custom color space conversion requirement.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeSC/M, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E, MachXO5-NX, Avant-G, Avant-X 

Image Processing, JPEG CODEC, Lattice mVision, UAVs, Automotive 

Reference Design

RGMII to GMII Bridge Reference Design

Lattice RGMII to GMII Bridge Reference Design provides a bi-directional bridge function for transferring data between RGMII and GMII.

LatticeECP3, ECP5 / ECP5-5G, CertusPro-NX, MachXO5-NX 

Ethernet, X/S/RGMII, Defense 

IP Core

PCI Express Endpoint Core

Provides a PCI Express x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer

ECP5 / ECP5-5G, LatticeECP3 

Bus Controllers, PCIe, Defense, Automotive, PCIe Bundle 

IP Core

LatticeMico32 Open, Free 32-Bit Soft Processor

A 32-bit Harvard, RISC architecture soft microprocessor, available for free with an open IP core license. Many compatible modules and IP are available.

LatticeECP3, LatticeXP2, LatticeECP2/M 

GPIO Control, Mico, Soft Processor, UART, Wishbone, TOR Switch, Defense 

IP Core

SGMII and Gb Ethernet PCS IP Core

SGMII and Gb Ethernet PCS IP core is used as an interface for a discrete Ethernet PHY chip & can be used in bridging applications and/or PHY implementation.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X 

Data Communication, Ethernet, X/S/RGMII, Automotive, Ethernet Bundle 

IP Core

Coordinate Rotational Digital Computer (CORDIC) IP Core

The Lattice CORDIC IP uses full internal precision while allowing variable output precision with several choices for rounding.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeSC/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X 

DSP, Automotive, DSP Bundle