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  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    USB 2.0/3.2 IP Core
  • USB to I/O Aggregation and Bridging Reference Design

    Reference Design

    USB to I/O Aggregation and Bridging Reference Design

    USB to IO Bridging Reference Design Create plug-and-play peripheral expansion on USB-enabled FPGA & signal protocol conversion from USB to I2C, SPI, & GPIO.
    USB to I/O Aggregation and Bridging Reference Design
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
    Object Classification Reference Design
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • Timer/Counter IP Core

    IP Core

    Timer/Counter IP Core

    Timer/Counter IP used to track timeouts in the system. Target devices are Certus-NX and Crosslink-NX.
    Timer/Counter IP Core
  • Advanced CNN Accelerator IP

    IP Core

    Advanced CNN Accelerator IP

    Calculates full layers of Neural Network including convolution layer, pooling layer, batch normalization layer, and fully connected layer.
    Advanced CNN Accelerator IP
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • TSEMAC & SGMII Reference Design

    Reference Design

    TSEMAC & SGMII Reference Design

    Lattice TSEMAC & SGMII Reference Design implements 1G/100M/10M Ethernet application using a TSEMAC IP Core with a SGMII PCS IP Core in loopback mode.
    TSEMAC & SGMII Reference Design
  • Video Scaler IP Core

    IP Core

    Video Scaler IP Core

    The Lattice Video Scaler IP Core is used to scale up or scale down the resolution of a video stream.
    Video Scaler IP Core
  • FreeRTOS

    IP Core

    FreeRTOS

    FreeRTOS software included in Lattice Propel 2022.1 for RISC-V embedded processor available with real-time kernel and set of libraries.
  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification Reference Design
  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting AI
  • CNN Plus Accelerator IP Core

    IP Core

    CNN Plus Accelerator IP Core

    CNN Plus IP is a flexible accelerator IP that simplifies implementation of Ultra-Low power AI by leveraging capabilities of Lattice FPGAs.
    CNN Plus Accelerator IP Core
  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
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