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  • Scene Segmentation Reference Design

    Reference Design

    Scene Segmentation Reference Design

    Efficient and low power approach for implementing scene segmentation using Lattice CrossLink-NX FPGA
    Scene Segmentation Reference Design
  • Timer/Counter IP Core

    IP Core

    Timer/Counter IP Core

    Timer/Counter IP used to track timeouts in the system. Target devices are Certus-NX and Crosslink-NX.
    Timer/Counter IP Core
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    Propel IP Module: 32-bit RISC-V processor core with optional Timer and PIC sub-modules, connects via AHB-Lite bus to other Propel IP modules and more.
    RISC-V MC CPU IP Core
  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification Reference Design
  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting AI
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • CSI-2/DSI D-PHY Receiver

    IP Core

  • FPD-LINK Receiver

    IP Core

    FPD-LINK Receiver

    Modular MIPI/D-PHY IP - Converts FPD-LINK Video Streams to Pixel Clock Domain
    FPD-LINK Receiver
  • FPD-LINK Transmitter

    IP Core

    FPD-LINK Transmitter

    Modular MIPI/D-PHY IP - Convert Pixel Data Streams to an FPD-LINK Video Stream
    FPD-LINK Transmitter
  • SubLVDS Image Sensor Receiver

    IP Core

    SubLVDS Image Sensor Receiver

    Modular MIPI/D-PHY IP - Converts SubLVDS Image Sensor Video Stream to Pixel Clock Domain
    SubLVDS Image Sensor Receiver
  • Lattice Image Signal Processing Reference Design

    Reference Design

    Lattice Image Signal Processing Reference Design

    Configure an ECP5 FPGA-based ISP solution tailored to your Industrial, Medical, and Automotive application.
    Lattice Image Signal Processing Reference Design
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
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