Lattice Solutions

IP Core

FFT Compiler IP Core

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X 

Data Communication, DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

IP Core

FIR Filter Generator IP Core

This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.

ECP5 / ECP5-5G, LatticeECP3, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X 

DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

IP Core

Image Signal Processing IP Cores Suite

The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.

CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E 

AXI, AXI-Stream, AXI-Lite Interface, AWB, Camera, CCM, CFA Interpolation, Debayer, Image Processing, Image Signal Processing, Lattice mVision, RGB, Defense 

Reference Design

​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

USB to IO Bridging Reference Design Create plug-and-play peripheral expansion on USB-enabled FPGA & signal protocol conversion from USB to I2C, SPI, & GPIO.

CrossLink-NX 

USB, USB2, USB3, I2C, SPI, JTAG, LVDS, SLVS, FTDI 

IP Core

USB 2.0/3.2 IP Core

Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.

CrossLink-NX 

USB, USB2, USB3, AHB, AHB-L, AHB-Lite, AXI, I2C, SPI, JTAG, LVDS, SLVS, FTDI 

Reference Design

Object Classification Reference Design

The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.

CertusPro-NX, Avant-E, CrossLink-NX 

Machine Learning/AI, Lattice sensAI, Object Detection, Object Identification, Space 

IP Core

PCI Express for Nexus FPGAs

The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

APB, AHB, AHB-Lite, RTL, PCI, PCIe, Bus Controllers, Defense, Automotive, PCIe Bundle, SDR 

IP Core

RISC-V MC CPU IP Core

The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).

MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2, Avant-G, Avant-X, ECP5 / ECP5-5G 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2, Avant-G, Avant-X, ECP5 / ECP5-5G 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

RISC-V RX CPU IP Core

Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, Avant-G, Avant-X, ECP5 / ECP5-5G 

AHB-Lite, Soft Processor, RISC-V, RTOS, Lattice Propel, Defense, Automotive 

IP Core

Timer/Counter IP Core

The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.

Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 LP/HX, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2, MachXO3, MachXO3D, MachXO5-NX 

AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

IP Core

Tightly-Coupled Memory (TCM) IP Core

The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.

Avant-E, Avant-G, Avant-X, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX 

Embedded Ram, FIFO, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense 

IP Core

AHB-Lite to AXI4 Bridge IP Core

The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.

Avant-E, Avant-G, Avant-X, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

AHB-L, AHB-Lite, AXI4, Lattice Avant 

IP Core

AXI4 Interconnect Module

AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.

Avant-E, Avant-G, Avant-X, CrossLink-NX, MachXO5-NX, Certus-NX, CertusPro-NX 

AMBA, AXI4, AXI, AXI-Lite Interface, Lattice Avant 

Reference Design

TSEMAC & SGMII Reference Design

Lattice TSEMAC & SGMII Reference Design implements 1G/100M/10M Ethernet application using a TSEMAC IP Core with a SGMII PCS IP Core in loopback mode.

CertusPro-NX, CrossLink-NX 

Ethernet, X/S/RGMII, TSEMAC, APB 

IP Core

Video Scaler IP Core

The Lattice Video Scaler IP Core is used to scale up or scale down the resolution of a video stream.

CertusPro-NX, Certus-NX, CrossLink-NX 

Lattice Drive, AXI, AXI-Lite Interface, Video Scaling, Embedded Ram, DSP, DSP Bundle 

IP Core

FreeRTOS

FreeRTOS software included in Lattice Propel 2022.1 for RISC-V embedded processor available with real-time kernel and set of libraries.

Avant-E, MachXO5-NX, CertusPro-NX, Certus-NX, CrossLink-NX 

Lattice Propel, RTOS, RISC-V 

Reference Design

HyperRAM Memory Controller Reference Design

Implements First-Generation HyperRAM Specifications

CrossLink-NX 

HyperRAM, EBR 

Reference Design

SSPI Embedded Programming using RPi Reference Design

SSPI Embedded Programming reference design provides several benefits, such as low power consumption and reasonable CPU, GPU, and memory performance.

CertusPro-NX, CrossLink-NX, CrossLinkPlus, CrossLink, MachXO3, MachXO2 

SSPI, Raspberry Pi 

Reference Design

Scene Segmentation Reference Design

Efficient and low power approach for implementing scene segmentation using Lattice CrossLink-NX FPGA

CrossLink-NX 

Lattice sensAI, Machine Learning/AI, SPI, Object Counting, Object Segmentation, Image Processing, Camera, Defense