Lattice Solutions

Everything you need to quickly and easily complete your design

Solution Type

Device Support













Tags





















































Providers


  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • Simple Sigma-Delta ADC

    Reference Design

    Simple Sigma-Delta ADC

    Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
    Simple Sigma-Delta ADC
  • Local Interconnect Network (LIN)

    IP Core

    Local Interconnect Network (LIN)

    Transmits and receives complete LIN frames to perform serial communication according to the LIN protocol specification
    LIN 
    Local Interconnect Network (LIN)
  • UART - WISHBONE Compatible

    Reference Design

    UART - WISHBONE Compatible

    UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.
    UART - WISHBONE Compatible
  • Universal Asynchronous Receiver/Transmitter

    Reference Design

    Universal Asynchronous Receiver/Transmitter

    Fully configurable UART functionally compatible with the NS16450 UART
    Universal Asynchronous Receiver/Transmitter
  • SDR SDRAM Controller - Advanced

    Reference Design

    SDR SDRAM Controller - Advanced

    Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.
    SDR SDRAM Controller - Advanced
  • Cyclic Redundancy Check

    Reference Design

    Cyclic Redundancy Check

    Implements CRC generator and checker with polynomial orders from CRC-1 to CRC-64
    Cyclic Redundancy Check
  • BSCAN - Multiple Port Linker (BSCAN2)

    Reference Design

    BSCAN - Multiple Port Linker (BSCAN2)

    Implements an IEEE 1149.1 compliant Boundary Scan port on an FPGA. Multiple scan ports are linked together feeing into the IEEE 1149.1 port.
    BSCAN - Multiple Port Linker (BSCAN2)
  • I2C Bus Controller for Serial EEPROMs

    Reference Design

    I2C Bus Controller for Serial EEPROMs

    Provides an interface between standard microprocessors and I2C Serial EEPROM devices
    I2C Bus Controller for Serial EEPROMs
  • I2C Slave/Peripheral

    Reference Design

    I2C Slave/Peripheral

    Implements an I2C slave module in a FPGA or CPLD. Follows the I2C specification to provide device addressing, read/write operation and acknowledgment
    I2C Slave/Peripheral
  • LED/OLED Driver

    Reference Design

    LED/OLED Driver

    Drive an LED via WISHBONE bus. Default is targeted to a GM1WA55311A LED but can be used to control other LEDs or OLEDs with similar functions.
    LED/OLED Driver
  • SPI Controller - WISHBONE Compatible

    Reference Design

    SPI Controller - WISHBONE Compatible

    Provides an interface between a microprocessor with a WISHBONE bus and external SPI devices.
    SPI Controller - WISHBONE Compatible
  • Single-Wire Controller for Digital Temp. Sensors

    Reference Design

    Single-Wire Controller for Digital Temp. Sensors

    Implements a Single Wire controller connected to a WISHBONE bus. Provides an example communicating to a Temperature Sensor.
    Single-Wire Controller for Digital Temp. Sensors
  • I2S Controller with WISHBONE Interface

    Reference Design

  • NOR Flash Memory Controller - WISHBONE Compatible

    Reference Design

    NOR Flash Memory Controller - WISHBONE Compatible

    Provides a NOR flash memory controller through WISHBONE bus. It supports several common operational modes of a NOR flash
    NOR Flash Memory Controller - WISHBONE Compatible
  • LPC (Low Pin Count) Bus Controller

    Reference Design

    LPC (Low Pin Count) Bus Controller

    Implements a Low Pin Count bus controller - based on the Intel Low Pin Count Interface Specification (version 1.1)
    LPC (Low Pin Count) Bus Controller
  • I2C Slave to SPI Master Bridge

    Reference Design

    I2C Slave to SPI Master Bridge

    Implements an I2C slave to SPI master bridge.
    I2C Slave to SPI Master Bridge
  • Page 1 of 3
    First Previous
    1 2 3
    Next Last
    Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.