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General Purpose
Includes all ECP
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Avant-E (5)
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TOR Switch (2)
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Video Tx/Rx (9)
Providers
Lattice (13)
Clear All
IP Core
Timer/Counter IP Core
The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.
Certus-NX
,
CrossLink-NX
,
Avant-E
,
Avant-G
,
Avant-X
,
CertusPro-NX
,
CrossLink
,
CrossLinkPlus
,
ECP5 / ECP5-5G
,
iCE40 LP/HX
,
iCE40 Ultra / UltraLite
,
iCE40 UltraPlus
,
LatticeECP2/M
,
LatticeECP3
,
LatticeSC/M
,
LatticeXP2
,
Mach-NX
,
MachXO
,
MachXO2
,
MachXO3
,
MachXO3D
,
MachXO5-NX
AMBA
,
Lattice Propel
,
Lattice Diamond
,
Lattice Radiant
,
APB
,
AHB-Lite
,
Lattice Sentry
,
Lattice Sentry PFR IP Package
,
Security
Reference Design
SSPI Embedded Programming using RPi Reference Design
SSPI Embedded Programming reference design provides several benefits, such as low power consumption and reasonable CPU, GPU, and memory performance.
CertusPro-NX
,
CrossLink-NX
,
CrossLinkPlus
,
CrossLink
,
MachXO3
,
MachXO2
SSPI
,
Raspberry Pi
IP Core
Byte to Pixel Converter IP Core
Byte-to-Pixel Converter IP converts CSI-2/DSI standard based video payload packets from D-PHY Receiver Module output to pixel format.
CrossLink
,
CrossLinkPlus
,
CrossLink-NX
,
Certus-NX
,
CertusPro-NX
,
Avant-E
,
MachXO5-NX
,
Avant-G
,
Avant-X
MIPI
,
Modular MIPI/D-PHY
,
Parallel Video
,
Video Tx/Rx
,
Lattice mVision
,
Home Control Appliances & Security
,
IoT & Wearables
,
Notebooks & PCs
,
Printers
,
Smart Toys & Robots
,
Tablets
,
Guidance Systems
,
Automotive
,
Space
,
MIPI Bundle
IP Core
CSI-2/DSI D-PHY Receiver IP Core
Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
CrossLink
,
CrossLinkPlus
,
CrossLink-NX
,
Certus-NX
,
CertusPro-NX
,
MachXO5-NX
,
Avant-E
,
Avant-G
,
Avant-X
CSI-2
,
DSI
,
MIPI
,
Modular MIPI/D-PHY
,
Video Tx/Rx
,
Lattice mVision
,
AR / VR & Drones
,
Home Control Appliances & Security
,
IoT & Wearables
,
Notebooks & PCs
,
Printers
,
Smart Toys & Robots
,
Tablets
,
Automotive
,
MIPI Bundle
IP Core
Pixel to Byte Converter IP Core
Converts one, two, four, six, eight, or ten pixels per pixel clock into MIPI D-PHY byte packet compatible format
CrossLink
,
CrossLinkPlus
,
CrossLink-NX
,
Certus-NX
,
CertusPro-NX
,
Avant-E
,
MachXO5-NX
,
Avant-G
,
Avant-X
CSI-2
,
MIPI
,
Modular MIPI/D-PHY
,
Parallel Video
,
Video Tx/Rx
,
Lattice mVision
,
Home Control Appliances & Security
,
IoT & Wearables
,
Notebooks & PCs
,
Printers
,
Smart Toys & Robots
,
Tablets
,
Guidance Systems
,
Automotive
,
MIPI Bundle
IP Core
SubLVDS Image Sensor Receiver IP Core
The subLVDS interface is primarily used in image sensors, integrating one clock pair and one or more data pairs.
CrossLink
,
CrossLinkPlus
,
CrossLink-NX
,
Certus-NX
,
CertusPro-NX
,
MachXO5-NX
,
Avant-E
,
Avant-G
,
Avant-X
LVDS Video
,
MIPI
,
Modular MIPI/D-PHY
,
Video Tx/Rx
,
Lattice mVision
,
Automotive
,
MIPI Bundle
Reference Design
1 to N MIPI CSI-2/DSI Duplicator Reference Design
The 1 to N MIPI CSI-2DSI Duplicator reference design stream on one RX channel is duplicated and sent out on one to four TX channels.
CrossLink
,
CrossLinkPlus
,
CrossLink-NX
,
CertusPro-NX
CSI-2
,
MIPI
,
Modular MIPI/D-PHY
,
Lattice mVision
,
DSI
,
Video Tx/Rx
,
AR / VR & Drones
,
Home Control Appliances & Security
,
IoT & Wearables
,
Notebooks & PCs
,
Printers
,
Smart Toys & Robots
,
Tablets
,
UAVs
,
Automotive
Reference Design
MIPI CSI-2 Virtual Channel Aggregation with CrossLink-NX
Modular MIPI/D-PHY Reference Design - Adaptable and flexible solution combines multiple MIPI CSI-2 inputs to a single CSI-2 output stream.
CrossLink
,
CrossLinkPlus
,
CrossLink-NX
CSI-2
,
MIPI
,
Modular MIPI/D-PHY
,
Lattice mVision
,
Signal Aggregation
,
Video Tx/Rx
,
Video Aggregation
,
AR / VR & Drones
,
Home Control Appliances & Security
,
IoT & Wearables
,
Notebooks & PCs
,
Printers
,
Smart Toys & Robots
,
Tablets
,
Defense
,
Automotive
Reference Design
MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
CrossLink
,
CrossLinkPlus
,
CrossLink-NX
,
CertusPro-NX
LVDS Video
,
MIPI
,
Modular MIPI/D-PHY
,
Lattice mVision
,
Video Tx/Rx
,
CSI-2
,
DSI
,
AR / VR & Drones
,
Home Control Appliances & Security
,
IoT & Wearables
,
Notebooks & PCs
,
Printers
,
Smart Toys & Robots
,
Tablets
,
Automotive
Reference Design
N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation
Modular MIPI/D-PHY Reference Design - Aggregate multiple MIPI CSI-2 inputs up to 5 channels horizontally line by line to a single CSI-2 output
CrossLink
,
CrossLinkPlus
,
CrossLink-NX
CSI-2
,
MIPI
,
Modular MIPI/D-PHY
,
Lattice mVision
,
Signal Aggregation
,
Video Tx/Rx
,
Video Aggregation
,
AR / VR & Drones
,
Home Control Appliances & Security
,
IoT & Wearables
,
Notebooks & PCs
,
Printers
,
Smart Toys & Robots
,
Tablets
,
Defense
,
Automotive
Reference Design
SubLVDS to MIPI CSI-2 Image Sensor Bridge
Modular MIPI/D-PHY Reference Design - Complete solution integrates the Pixel to Byte Converter, SubLVDS Image Sensor Recevier and CSI-2/DSI D-PHY Transmitter
CrossLink
,
CrossLinkPlus
CSI-2
,
LVDS Video
,
MIPI
,
Modular MIPI/D-PHY
,
Lattice mVision
,
Video Tx/Rx
,
Automotive
Reference Design
Soft I2C Bus Master
Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
CrossLink
,
CrossLink-NX
,
CrossLinkPlus
,
ECP5 / ECP5-5G
,
iCE40 UltraPlus
,
LatticeECP3
,
MachXO2
,
MachXO3
,
Mach-NX
5G
,
Computing
,
IoT
,
TOR Switch
,
Bus Controllers
,
I2C
Reference Design
Soft I2C Slave Peripheral
Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
CrossLink
,
CrossLink-NX
,
CrossLinkPlus
,
ECP5 / ECP5-5G
,
iCE40 UltraPlus
,
LatticeECP3
,
MachXO2
,
MachXO3
5G
,
Computing
,
IoT
,
TOR Switch
,
Bus Controllers
,
I2C
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