Lattice Solutions

IP Core

RISC-V MC CPU IP Core

The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).

MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2, Avant-G, Avant-X 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive 

IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2, Avant-G, Avant-X 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive 

IP Core

Timer/Counter IP Core

The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.

Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 LP/HX, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2, MachXO3, MachXO3D, MachXO5-NX 

AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

Reference Design

MPESTI Initiator Reference Design

MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.

Avant-E, MachXO5-NX, MachXO3, MachXO3D 

MPESTI, UART, APB, AHB 

Reference Design

APB to AHB-Lite Bridge Reference Design

The APB to AHB-Lite Bridge Reference Design provides an interface between the low power APB and the high-speed AHB-Lite.

MachXO3D, MachXO3, MachXO2 

APB, AHB, AMBA 

IP Core

DC-SCM LVDS Tunneling Protocol and Interface IP Core

LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.

MachXO3, MachXO3D, MachXO5-NX 

CRC, LVDS, LTPI, AMBA, APB, Lattice Diamond, Lattice Radiant 

Reference Design

LVDS Tunneling Protocol and Interface Reference Design

The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.

MachXO5-NX, MachXO3D, MachXO3, Mach-NX 

CRC, LVDS, I2C, GPIO, UART, LTPI, AMBA, APB, Lattice Diamond, Lattice Propel 

Reference Design

I2C to APB Bridge Reference Design

With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.

MachXO2, MachXO3, MachXO3D 

I2C, APB, AMBA, AHB 

Reference Design

Generic Soft SPI Master Controller Reference Design

Provides an interface between a generic processor with parallel bus interface and external SPI devices.

MachXO2, MachXO3, LatticeECP3, ECP5 / ECP5-5G, CrossLink, CrossLink-NX, iCE40 UltraPlus 

SPI, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3, Mach-NX 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

IP Core

System Memory Module IP Core

Propel IP Module: Configures Embedded Block RAMs or Distributed Memory interfaces and connects to the AHB-Lite bus.

Avant-E, CertusPro-NX, Certus-NX, CrossLink-NX, Mach-NX, MachXO3D, MachXO3, MachXO2 

Embedded Ram, AHB-Lite, AMBA, Lattice Propel, TOR Switch, Automotive 

Reference Design

I2C Bus Master

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device

MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, Platform Manager, ECP5 / ECP5-5G, MachXO3 

Bus Controllers, I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

I2C Master - WISHBONE Compatible

Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus

MachXO, MachXO2, LatticeXP2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 

I2C, Wishbone, Bus Controllers, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

IP Core

I3C-S-MIPI-I3C-Basic-Slave-Controller

Highly featured, SDR-Capable and HDR-Tolerant Slave controller. Supports hot-join, in-band interrupts, & dynamic addressing. Works to any Lattice FPGA device.

MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 

I3C, MIPI 

IP Core

JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

Scalable, ultra-high throughput 8/12-bit JPEG decoder. Ideal for low-latency motion-Jpeg streaming. Full-HD or Ultra-HD capable depending on the device.

MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 

Data Compression, JPEG, JPEG CODEC 

IP Core

JPEG-DX-S - Baseline and Extended JPEG Decoder

Compact, 8bit and 12bit per color, JPEG decoder. Ideal for low-latency motion-Jpeg streaming.

MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 

Data Compression, JPEG, JPEG CODEC 

IP Core

JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

Scalable, ultra-high throughput 8/12-bit encoder. Highly configurable with advanced bit-rate control. Ideal for low-latency motion-Jpeg streaming.

MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 

Data Compression, JPEG, JPEG CODEC 

IP Core

JPEG-EX-S - Baseline and Extended JPEG Encoder

Compact, 8bit and 12bit per color, JPEG encoder. Highly configurable with advanced bit-rate control features. Ideal for low-latency motion-Jpeg streaming.

MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 

Data Compression, JPEG, JPEG CODEC 

IP Core

SPMI-CTRL - MIPI SPMI Master or Slave Controller

Highly featured, easy-to-use master or slave controller supporting the latest version of the MIPI-SPMI specification. Portable to any Lattice FPGA device

MachXO2, MachXO3, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP3, ECP5 / ECP5-5G, Certus-NX, CrossLink-NX 

Power Management Bus, Power Management, MIPI, SPMI