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  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, Platform Manager, ECP5 / ECP5-5G, MachXO3 
    Bus Controllers, I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 
    I2C Bus Master
  • UART Reference Design

    Reference Design

    UART Reference Design

    The UART reference design describes a fully configurable UART optimized for and implemented in a variety of Lattice devices.
    ispMACH 4000ZE, MachXO, LatticeXP2, Platform Manager, MachXO5-NX, MachXO2 
    Bus Controllers, UART 
    UART Reference Design
  • I2C Slave/Peripheral

    Reference Design

    I2C Slave/Peripheral

    Implements an I2C slave module in a FPGA or CPLD. Follows the I2C specification to provide device addressing, read/write operation and acknowledgment
    LatticeECP3, LatticeXP2, MachXO, Platform Manager, ispMACH 4000ZE, ECP5 / ECP5-5G 
    I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 
    I2C Slave/Peripheral
  • I2C Slave to SPI Master Bridge

    Reference Design

    I2C Slave to SPI Master Bridge

    Implements an I2C slave to SPI master bridge.
    MachXO, Platform Manager 
    I2C, SPI, TOR Switch 
    I2C Slave to SPI Master Bridge
  • BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

    Reference Design

    BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

    A multiple boundary scan test access port (TAP) addressable buffer function that can be accessed through a standard IEEE 1149.1 interface
    LatticeXP2, ispMACH 4000ZE, MachXO, ispMACH 4000V/B/C/Z, Platform Manager 
    Boundary Scan, IEEE 1149.1, TOR Switch 
    BSCAN - Multiple Port Addressable Buffer (BSCAN-1)
  • Power Management Bus

    Reference Design

    Power Management Bus

    Implements the Data Link Layer protocol of the Power Management Bus, conneting to a WISHBONE interface
    MachXO, MachXO2, Platform Manager 
    Bus Controllers, Mixed-Signal, Power Management Bus, Wishbone, Defense 
    Power Management Bus
  • Long Delay Timer Functions

    Reference Design

    Long Delay Timer Functions

    Demontrates the techniques necessary for generating long duration timeouts. Timeouts of 2, 4 8 or 16 seconds are demonstrated
    Platform Manager 
    TOR Switch 
    Long Delay Timer Functions
  • Platform Manager Utility Function Core IP

    IP Core

    Platform Manager Utility Function Core IP

    Supports Fault Logging and Enhanced Closed-loop Trim power management functions.
    Platform Manager 
    Mixed-Signal, Power Management, TOR Switch, Defense 
    Platform Manager Utility Function Core IP
  • SPI GPIO Expander

    Reference Design

    SPI GPIO Expander

    Expand microprocessor general purpose I/O ports with a Serial Peripheral Interface (SPI)
    Platform Manager, MachXO, ispMACH 4000ZE 
    GPIO Control, Signal Aggregation, Soft Processor, SPI, TOR Switch 
    SPI GPIO Expander
  • GPIO Expander

    Reference Design

    GPIO Expander

    Provides a solution that uses a Lattice PLD as a GPIO Expander
    LatticeECP3, MachXO, LatticeXP2, ispMACH 4000ZE, Platform Manager 
    GPIO Control, Signal Aggregation, TOR Switch 
    GPIO Expander
  • Circuit Board Fault Monitoring and Logging

    Reference Design

    Circuit Board Fault Monitoring and Logging

    Records the supply fault condition in non-volatile memory so the fault(s) can read back at a later time
    Platform Manager 
    Mixed-Signal, Power Management, SPI Flash, Guidance Systems 
    Circuit Board Fault Monitoring and Logging
  • Closed Loop Power Supply Trimming

    Reference Design

    Closed Loop Power Supply Trimming

    Monitor and control different power supplies. Improve supply precision to <1.0% output error. Set pre-determined output levels.
    Platform Manager 
    Guidance Systems 
    Closed Loop Power Supply Trimming
  • SPI Peripheral

    Reference Design

    SPI Peripheral

    Implements a Serial Peripheral Interface (SPI) slave device interface that provides full-duplex, synchronous, serial communication with a SPI master
    MachXO, ispMACH 4000ZE, Platform Manager 
    Bus Controllers, SPI, TOR Switch 
    SPI Peripheral
  • ADC Temperature Measurement Readout

    Reference Design

    ADC Temperature Measurement Readout

    Demonstrates the input of ambient temperature using an input voltage developed using an external resistor/thermistor and interface to the on-chip ADC using I2C
    Platform Manager 
    ADC/DAC, I2C, Mixed-Signal, Temperature Sensor, Guidance Systems 
    ADC Temperature Measurement Readout
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