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  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification Reference Design
  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting AI
  • Convolutional Neural Network (CNN) Accelerator IP

    IP Core

    Convolutional Neural Network (CNN) Accelerator IP

    Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    Convolutional Neural Network (CNN) Accelerator IP
  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • Lattice Image Signal Processing Reference Design

    Reference Design

    Lattice Image Signal Processing Reference Design

    Configure an ECP5 FPGA-based ISP solution tailored to your Industrial, Medical, and Automotive application.
    Lattice Image Signal Processing Reference Design
  • Tri-Speed Ethernet MAC IP Core

    IP Core

    Tri-Speed Ethernet MAC IP Core

    The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor
    Tri-Speed Ethernet MAC IP Core
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    Soft I2C Bus Master
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    Soft I2C Slave Peripheral
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • DDR3 PHY

    IP Core

    DDR3 PHY

    Connects a DDR3 memory Controller (MC) to a DDR3 memory device (JESD79-3). Contains all the logic required for functions dependent on FPGA DDR IO primitives
    DDR3 PHY
  • DDR3 SDRAM Controller

    IP Core

    DDR3 SDRAM Controller

    General-purpose complete memory controller interfaces with industry standard DDR3 memory (JESD79-3 Standard), and provides a generic command interface
    DDR3 SDRAM Controller
  • LPDDR3 SDRAM Controller

    IP Core

    LPDDR3 SDRAM Controller

    A general-purpose memory controller that interfaces with industry standard LPDDR3 memory devices and modules compliant with the JESD-209.3 specification
    LPDDR3 SDRAM Controller
  • RPC DRAM Controller

    IP Core

    RPC DRAM Controller

    Implements an FPGA-based RPC DRAM Memory Controller. Up to 400 MHz / 800 Mbps with memory data path widths of -16, and -32 bits - AXI interface.
    RPC DRAM Controller
  • Color Space Converter (CSC) IP Core

    IP Core

    Color Space Converter (CSC) IP Core

    The Lattice Color Space Converter IP Core is widely parameterizable and can support any custom color space conversion requirement.
    Color Space Converter (CSC) IP Core
  • RGMII to GMII Bridge Reference Design

    Reference Design

    RGMII to GMII Bridge Reference Design

    Lattice RGMII to GMII Bridge Reference Design provides a bi-directional bridge function for transferring data between RGMII and GMII.
    RGMII to GMII Bridge Reference Design
  • PCI Express Endpoint Core

    IP Core

    PCI Express Endpoint Core

    Provides a PCI Express x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer
    PCI Express Endpoint Core
  • PCI Express x1, x4 Root Complex Lite IP Core

    IP Core

    PCI Express x1, x4 Root Complex Lite IP Core

    Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
    PCI Express x1, x4 Root Complex Lite IP Core
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