Lattice Solutions

IP Core

Timer/Counter IP Core

The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.

Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 LP/HX, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2, MachXO3, MachXO3D, MachXO5-NX 

AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

Reference Design

Human Face Identification Reference Design

Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.

ECP5 / ECP5-5G, CertusPro-NX, CrossLink-NX 

Object Detection, Object Identification, Lattice sensAI, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, UAVs 

Reference Design

Object Counting AI

An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine

ECP5 / ECP5-5G, CrossLink-NX 

Machine Learning/AI, Lattice sensAI, Object Counting, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, Automotive 

IP Core

Convolutional Neural Network (CNN) Accelerator IP

Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.

ECP5 / ECP5-5G 

Machine Learning/AI, Lattice sensAI, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense 

IP Core

Helion IONOS Image Signal Processing IP Portfolio

Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.

MachXO, LatticeXP2, LatticeECP3, CrossLink, ECP5 / ECP5-5G, CrossLink-NX 

HDR, Image Processing, Video Tx/Rx, Lattice mVision, Automotive 

Reference Design

Lattice Image Signal Processing Reference Design

Configure an ECP5 FPGA-based ISP solution tailored to your Industrial, Medical, and Automotive application.

ECP5 / ECP5-5G, CrossLink 

Image Signal Processing, Lattice mVision 

IP Core

Tri-Speed Ethernet MAC IP Core

The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, LatticeSC/M, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E 

Connectivity IP Suite, Data Communication, Ethernet, Value IP Suite, Defense, Automotive, APB, AXI, AXI-Lite Interface, AHB 

Reference Design

Generic Soft SPI Master Controller Reference Design

Provides an interface between a generic processor with parallel bus interface and external SPI devices.

MachXO2, MachXO3, LatticeECP3, ECP5 / ECP5-5G, CrossLink, CrossLink-NX, iCE40 UltraPlus 

SPI, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3, Mach-NX 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

I2C Bus Master

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device

MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, Platform Manager, ECP5 / ECP5-5G, MachXO3 

Bus Controllers, I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

I2C Master - WISHBONE Compatible

Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus

MachXO, MachXO2, LatticeXP2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 

I2C, Wishbone, Bus Controllers, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

IP Core

DDR3 PHY

Connects a DDR3 memory Controller (MC) to a DDR3 memory device (JESD79-3). Contains all the logic required for functions dependent on FPGA DDR IO primitives

ECP5 / ECP5-5G, LatticeECP3, CrossLink-NX, Certus-NX, CertusPro-NX 

Connectivity IP Suite, DDR SDRAM, Automotive 

IP Core

DDR3 SDRAM Controller

General-purpose complete memory controller interfaces with industry standard DDR3 memory (JESD79-3 Standard), and provides a generic command interface

LatticeECP3, ECP5 / ECP5-5G, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

Connectivity IP Suite, DDR SDRAM, PCIe IP Suite, Value IP Suite, Video IP Suite, Automotive 

IP Core

LPDDR3 SDRAM Controller

A general-purpose memory controller that interfaces with industry standard LPDDR3 memory devices and modules compliant with the JESD-209.3 specification

ECP5 / ECP5-5G 

Connectivity IP Suite, DDR SDRAM, PCIe IP Suite, Video IP Suite, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

IP Core

RPC DRAM Controller

Implements an FPGA-based RPC DRAM Memory Controller. Up to 400 MHz / 800 Mbps with memory data path widths of -16, and -32 bits - AXI interface.

ECP5 / ECP5-5G 

DDR SDRAM, AXI 

IP Core

Color Space Converter (CSC) IP Core

The Lattice Color Space Converter IP Core is widely parameterizable and can support any custom color space conversion requirement.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeSC/M, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E, MachXO5-NX, Avant-G, Avant-X 

Image Processing, JPEG CODEC, Video IP Suite, Lattice mVision, UAVs, Automotive 

Reference Design

RGMII to GMII Bridge Reference Design

Lattice RGMII to GMII Bridge Reference Design provides a bi-directional bridge function for transferring data between RGMII and GMII.

LatticeECP3, ECP5 / ECP5-5G, CertusPro-NX, MachXO5-NX 

Ethernet, X/S/RGMII, Defense 

IP Core

PCI Express Endpoint Core

Provides a PCI Express x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer

ECP5 / ECP5-5G, LatticeECP3 

Bus Controllers, Connectivity IP Suite, PCIe, PCIe IP Suite, Defense, Automotive 

IP Core

PCI Express x1, x4 Root Complex Lite IP Core

Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M 

Connectivity IP Suite, PCIe, PCIe IP Suite, Guidance Systems, Automotive