Lattice Solutions

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  • CNN Accelerator IP

    IP Core

    CNN Accelerator IP

    Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Accelerator IP
  • CNN Compact Accelerator IP

    IP Core

    CNN Compact Accelerator IP

    Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
    CNN Compact Accelerator IP
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • Byte to Pixel Converter

    IP Core

    Byte to Pixel Converter

    Modular MIPI/D-PHY IP - Converts Parallel Data From a D-PHY Receiver into Pixel Format
    Byte to Pixel Converter
  • CSI-2/DSI D-PHY Receiver

    IP Core

    CSI-2/DSI D-PHY Receiver

    Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Receiver
  • CSI-2/DSI D-PHY Transmitter

    IP Core

    CSI-2/DSI D-PHY Transmitter

    Modular MIPI/D-PHY IP - PHY for transmitting MIPI CSI-2/DSI Data. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Transmitter
  • FPD-LINK Receiver

    IP Core

    FPD-LINK Receiver

    Modular MIPI/D-PHY IP - Converts FPD-LINK Video Streams to Pixel Clock Domain
    FPD-LINK Receiver
  • FPD-LINK Transmitter

    IP Core

    FPD-LINK Transmitter

    Modular MIPI/D-PHY IP - Convert Pixel Data Streams to an FPD-LINK Video Stream
    FPD-LINK Transmitter
  • Pixel to Byte Converter

    IP Core

    Pixel to Byte Converter

    Modular MIPI/D-PHY IP - Converts Pixel Format Data to Parallel Byte Format
    Pixel to Byte Converter
  • SubLVDS Image Sensor Receiver

    IP Core

    SubLVDS Image Sensor Receiver

    Modular MIPI/D-PHY IP - Converts SubLVDS Image Sensor Video Stream to Pixel Clock Domain
    SubLVDS Image Sensor Receiver
  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
  • DisplayPort IP

    IP Core

    DisplayPort IP

    Lattice has partnered with Bitec to bring the DisplayPort 1.4a compliant IP Core (with eDP 1.4 support) to the ECP5 FPGA. Supports resolutions of up to 1080p60
  • Tri-Speed Ethernet MAC Core IP

    IP Core

    Tri-Speed Ethernet MAC Core IP

    Transmits and receives data between a host processor and an Ethernet network. IEEE 802.3 compliant. Supports 10/100/1000 operation.
    Tri-Speed Ethernet MAC Core IP
  • GPIO IP Core

    IP Core

    GPIO IP Core

    Detects and controls GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB).
    GPIO IP Core
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Communicates with external SPI slave devices. Configurable data width, FIFO Tx/Rx depth, polarity, clocking modes and memory interface.
    SPI Master IP Core
  • SPI Slave IP Core

    IP Core

    SPI Slave IP Core

    Interfaces to SPI bus. Configurable data width, polarity, clocking modes and memory interface.
    SPI Slave IP Core
  •  I2C Slave IP Core

    IP Core

    I2C Slave IP Core

    Interfaces to an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
     I2C Slave IP Core
  • I2C Master IP Core

    IP Core

    I2C Master IP Core

    Controls an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
    I2C Master IP Core
  • DDR3 PHY

    IP Core

    DDR3 PHY

    Connects a DDR3 memory Controller (MC) to a DDR3 memory device (JESD79-3). Contains all the logic required for functions dependent on FPGA DDR IO primitives
    DDR3 PHY
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