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  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    A reference design for implementing object classification based on Mobilenet NN model running on Lattice CertusPro-NX low power FPGA
    Object Classification Reference Design
  • Hand Gesture Detection

    Reference Design

    Hand Gesture Detection

    Implements a low power AI based system to detect hand gestures using an IR image sensor
    Hand Gesture Detection
  • Lattice Sentry Root of Trust Reference Design for MachXO3D

    Reference Design

    Lattice Sentry Root of Trust Reference Design for MachXO3D

    This design utilizes Lattice Sentry IP to help you develop and test a complete NIST 800-193-compliant PFR solution. You can modify to suit your specific needs.
    Lattice Sentry Root of Trust Reference Design for MachXO3D
  • Key Phrase Detection

    Reference Design

    Key Phrase Detection

    Continuous searches for a key phrase utterance via a digital MEMS microphone. Can be re-configured to work with any trained word or phrase.
    Key Phrase Detection
  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification Reference Design
  • Human Presence Detection

    Reference Design

    Human Presence Detection

    Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
    Human Presence Detection
  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting AI
  • Lattice Image Signal Processing Reference Design

    Reference Design

    Lattice Image Signal Processing Reference Design

    Configure an ECP5 FPGA-based ISP solution tailored to your Industrial, Medical, and Automotive application.
    Lattice Image Signal Processing Reference Design
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
  • MIPI DSI/CSI-2 to Parallel Bridge Reference Design

    Reference Design

    MIPI DSI/CSI-2 to Parallel Bridge Reference Design

    Modular MIPI/D-PHY Reference Design - Converts MIPI CSI-2 input to Parallel data type output
    MIPI DSI/CSI-2 to Parallel Bridge Reference Design
  • Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

    Reference Design

  • SubLVDS to MIPI CSI-2 Image Sensor Bridge

    Reference Design

    SubLVDS to MIPI CSI-2 Image Sensor Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Pixel to Byte Converter, SubLVDS Image Sensor Recevier and CSI-2/DSI D-PHY Transmitter
    SubLVDS to MIPI CSI-2 Image Sensor Bridge
  • Single Wire Aggregation

    Reference Design

    Single Wire Aggregation

    Use a low-cost FPGA to aggregate multiple data streams such as I2C, UART, I2S and GPIO in TDM fashion, transmit a over single wire, and de-aggregate.
    Single Wire Aggregation
  • 8N1 UART Transceiver Reference Design

    Reference Design

    8N1 UART Transceiver Reference Design

    8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU
    8N1 UART Transceiver Reference Design
  • Multi-Channel Motor Control with Predictive Maintenance

    Reference Design

    Multi-Channel Motor Control with Predictive Maintenance

    This design incorporates a RISC-V CPU and processing subsystem supporting multi-channel Motor Control with Predictive Maintenance.
    Multi-Channel Motor Control with Predictive Maintenance
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