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  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • eUSB 3.1 FMC

    Board

    eUSB 3.1 FMC

    eUSB 3.1 FMC board is to validate USB 3.1 functionality with FPGA’s inbuilt serial transceivers. It has ULPI PHY chip to validate USB 2.0 functionality.
    eUSB 3.1 FMC
  • eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    IP Core

    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    This IP core solution uses the CL-NX FPGA’s built-in transceiver for USB 3.1 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)
  • SLS I2C Master IP Core

    IP Core

    SLS I2C Master IP Core

    Ease to use I2C Master IP core from SLS. It comes with ready to use HAL driver, reference design and various documents.
    SLS I2C Master IP Core
  • USB 2.0 Device Controller IP Core (USB20SF)

    IP Core

    USB 2.0 Device Controller IP Core (USB20SF)

    USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
    USB 2.0 Device Controller IP Core (USB20SF)
  • USB 2.0 Device with FIFO Interface (USB20HF)

    IP Core

    USB 2.0 Device with FIFO Interface (USB20HF)

    USB20HF IP Core provides FIFO & ULPI interface. It supports High Speed and Full Speed functionality for 15 IN/OUT endpoints.
    USB 2.0 Device with FIFO Interface (USB20HF)
  • Vehicle Classification AI Demo

    Demo

    Vehicle Classification AI Demo

    Classifies vehicle types using a Convolutional Neural Network (CNN) Accelerator IP on the ECP5 FPGA. HDMI output uses color-coded bounding boxes.
    Vehicle Classification AI Demo
  • Tachysséma Développement 101 Module

    Board

    Tachysséma Développement 101 Module

    A versatile compact low-power stand-alone module with LPDDR4 & 10G SERDES. Excellent compact solution (27x47m) for embedded imaging and vision applications.
    Tachysséma Développement 101 Module
  • Tachysséma Développement 201 Board

    Board

    Tachysséma Développement 201 Board

    A powerful development board that makes development, testing and validation of FPGA CertusPro-NX projects easier and supports 10 GbE SerDes and LPDDR4 memory.
    Tachysséma Développement 201 Board
  • DPControl iCEVision Board

    Board

    DPControl iCEVision Board

    A highly flexible and expandable prototyping platform for vision based AI and many other applictions
    DPControl iCEVision Board
  • MAS LIFCL Evaluation Board

    Board

    MAS LIFCL Evaluation Board

    This modular, flexible and easy-to-use CrossLink-NX 17 board is designed for video applications, including CSI2 MIPI, LVDS HDMI (through PMOD).
    MAS LIFCL Evaluation Board
  • CRUVI Certus-NX Base Board

    Board

    CRUVI Certus-NX Base Board

    Evaluation and development with Certus-NX FPGA, included are CRUVI HS/LS interface and 100mil pin headers for user IO, on-board USB JTAG/UART.
    CRUVI Certus-NX Base Board
  • IceZero

    Board

    IceZero

    Low-cost general purpose platform for the RaspberryPi with 4 MBit SRAM and four 2 x 6 PMOD interfaces for 32 3.3V LVCMOS IOs. Powered/configured over the 2 x 20 Raspberry Pi header.
    IceZero
  • icoBoard

    Board

    icoBoard

    Pin-compatible with Raspberry Pi 2 - B. Contains an 8K LUT, 100 MHz Lattice FPGA, 8 MBit of SRAM. Programmable in Verilog by a complete open source FPGA toolchain.
    icoBoard
  • LXO2000

    Board

    LXO2000

    The TEL0001 "LXO2000" is a low cost FPGA module integrating a Lattice XO2-4000 and on-board USB/JTAG. It's compatible to the Arduino MKR standard.
    LXO2000
  • Ikva ML Accelerator IP Core

    IP Core

    Ikva ML Accelerator IP Core

    Powerful, scalable ML accelerator supporting 8-bit CNNs and 1-bit Binarized Neural Networks (BNNs), a rich software stack and computer vision models.
    Ikva ML Accelerator IP Core
  • Adjustable Counter Clock

    IP Core

    Adjustable Counter Clock

    The adjustable clock IP is a counter clock that can be adjusted with offset and drift corrections to follow another clock.
    Adjustable Counter Clock
  • DPC CCM – Color correction

    IP Core

    DPC CCM – Color correction

    DPC CCM is designed to reduce the difference between the spectral characteristics of an image sensor and the spectral response of the human eye.
    DPC CCM – Color correction
  • DPC Color Conversion

    IP Core

    DPC Color Conversion

    DPC Color Conversion allows real-time conversion of the RGB colour space into the YCbCr colour space.
    DPC Color Conversion
  • DPC Convolution 3x3

    IP Core

    DPC Convolution 3x3

    DPC Conv3x3 applies a kernel to a video stream, in real time, in order to obtain spatial filtering such as Sobel, Gaussian, Laplacian and more.
    DPC Convolution 3x3
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