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  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • eUSB 3.1 FMC

    Board

    eUSB 3.1 FMC

    eUSB 3.1 FMC board is to validate USB 3.1 functionality with FPGA’s inbuilt serial transceivers. It has ULPI PHY chip to validate USB 2.0 functionality.
    eUSB 3.1 FMC
  • eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    IP Core

    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    This IP core solution uses the CL-NX FPGA’s built-in transceiver for USB 3.1 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)
  • USB 2.0 Device Controller IP Core (USB20SF)

    IP Core

    USB 2.0 Device Controller IP Core (USB20SF)

    USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
    USB 2.0 Device Controller IP Core (USB20SF)
  • USB 2.0 Device with FIFO Interface (USB20HF)

    IP Core

    USB 2.0 Device with FIFO Interface (USB20HF)

    USB20HF IP Core provides FIFO & ULPI interface. It supports High Speed and Full Speed functionality for 15 IN/OUT endpoints.
    USB 2.0 Device with FIFO Interface (USB20HF)
  • Vehicle Classification AI Demo

    Demo

    Vehicle Classification AI Demo

    Classifies vehicle types using a Convolutional Neural Network (CNN) Accelerator IP on the ECP5 FPGA. HDMI output uses color-coded bounding boxes.
    Vehicle Classification AI Demo
  • IceZero

    Board

    IceZero

    Low-cost general purpose platform for the RaspberryPi with 4 MBit SRAM and four 2 x 6 PMOD interfaces for 32 3.3V LVCMOS IOs. Powered/configured over the 2 x 20 Raspberry Pi header.
    IceZero
  • icoBoard

    Board

    icoBoard

    Pin-compatible with Raspberry Pi 2 - B. Contains an 8K LUT, 100 MHz Lattice FPGA, 8 MBit of SRAM. Programmable in Verilog by a complete open source FPGA toolchain.
    icoBoard
  • LXO2000

    Board

    LXO2000

    The TEL0001 "LXO2000" is a low cost FPGA module integrating a Lattice XO2-4000 and on-board USB/JTAG. It's compatible to the Arduino MKR standard.
    LXO2000
  • Ikva ML Accelerator IP Core

    IP Core

    Ikva ML Accelerator IP Core

    Powerful, scalable ML accelerator supporting 8-bit CNNs and 1-bit Binarized Neural Networks (BNNs), a rich software stack and computer vision models.
    Ikva ML Accelerator IP Core
  • Trenz TEP0002-03-Pmod-compatible-motor-driver-board-15A-0-30V

    Board

    Trenz TEP0002-03-Pmod-compatible-motor-driver-board-15A-0-30V

    The Trenz Electronic TEP0002 is a Pmod compatible motor driver board and good for developing BLCD or CD motor driving software.
     
    Trenz TEP0002-03-Pmod-compatible-motor-driver-board-15A-0-30V
  • I3C-S-MIPI-I3C-Basic-Slave-Controller

    IP Core

    I3C-S-MIPI-I3C-Basic-Slave-Controller

    Highly featured, SDR-Capable and HDR-Tolerant Slave controller. Supports hot-join, in-band interrupts, & dynamic addressing. Works to any Lattice FPGA device.
    I3C-S-MIPI-I3C-Basic-Slave-Controller
  • JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    Scalable, ultra-high throughput 8/12-bit JPEG decoder. Ideal for low-latency motion-Jpeg streaming. Full-HD or Ultra-HD capable depending on the device.
    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder
  • JPEG-DX-S - Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-S - Baseline and Extended JPEG Decoder

    Compact, 8bit and 12bit per color, JPEG decoder. Ideal for low-latency motion-Jpeg streaming.
    JPEG-DX-S - Baseline and Extended JPEG Decoder
  • JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    Scalable, ultra-high throughput 8/12-bit encoder. Highly configurable with advanced bit-rate control. Ideal for low-latency motion-Jpeg streaming.
    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder
  • JPEG-EX-S - Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-S - Baseline and Extended JPEG Encoder

    Compact, 8bit and 12bit per color, JPEG encoder. Highly configurable with advanced bit-rate control features. Ideal for low-latency motion-Jpeg streaming.
    JPEG-EX-S - Baseline and Extended JPEG Encoder
  • SPMI-CTRL - MIPI SPMI Master or Slave Controller

    IP Core

    SPMI-CTRL - MIPI SPMI Master or Slave Controller

    Highly featured, easy-to-use master or slave controller supporting the latest version of the MIPI-SPMI specification. Portable to any Lattice FPGA device
    SPMI-CTRL - MIPI SPMI Master or Slave Controller
  • TSN-EP – TSN Ethernet Endpoint Controller

    IP Core

    TSN-EP – TSN Ethernet Endpoint Controller

    Highly flexible core supports timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, Qbv) and frame-preemption (IEEE 802.1Qbu, & 802.3br).
    TSN-EP – TSN Ethernet Endpoint Controller
  • UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    IP Core

    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    Standalone, processor-less operation with up to 32 Rx and 32 Tx channels. Supports DHCP, IGMP, ICMP, ARP with cache, Jumbo and super Jumbo IPv4 frames.
    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack
  • LIN - LIN Bus Master/Slave Controller

    IP Core

    LIN - LIN Bus Master/Slave Controller

    Production-proven core suitable for LIN 2.2 or earlier networks. Standard and Safety Enhanced (ISO 26262) versions. Portable to any Lattice FPGA.
    LIN - LIN Bus Master/Slave Controller
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