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  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT Compiler IP Core
  • FIR Filter Generator IP Core

    IP Core

    FIR Filter Generator IP Core

    This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
    FIR Filter Generator IP Core
  • 10Gb Ethernet MAC+PHY IP Core

    IP Core

    10Gb Ethernet MAC+PHY IP Core

    The Lattice 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    10Gb Ethernet MAC+PHY IP Core
  • MACsec AES256-GCM, High-speed (XIP1213H)

    IP Core

    MACsec AES256-GCM, High-speed (XIP1213H)

    The high-speed MACsec IP core implements the MACsec protocol as standardized in IEEE 802.1AE-2018, defining a security infrastructure for OSI model Layer 2 traffic.
    MACsec AES256-GCM, High-speed (XIP1213H)
  • QSPI Flash Controller IP Core

    IP Core

    QSPI Flash Controller IP Core

    The QSPI Flash Controller IP allows communication with multiple external SPI flash devices using standard, extended dual/quad, dual, or quad SPI protocols.
  • ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    IP Core

    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    ML-KEM-512/768/1024 is an IP core for post-quantum Key Encapsulation Mechanism (KEM), optimized for a good balance between speed and resource requirements.
    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • PCI Express for Avant FPGAs

    IP Core

    PCI Express for Avant FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Avant FPGAs
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • AHB-Lite to AXI4 Bridge IP Core

    IP Core

    AHB-Lite to AXI4 Bridge IP Core

    The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.
    AHB-Lite to AXI4 Bridge IP Core
  • AXI4 Interconnect Module

    IP Core

    AXI4 Interconnect Module

    AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.
    AXI4 Interconnect Module
  • AXI4 Multi Port Bridge for Memory Controller IP Core

    IP Core

    AXI4 Multi Port Bridge for Memory Controller IP Core

    The AXI4 Multi Port Bridge for Memory Controller (MPMC) IP connects multiple external managers to a single memory controller.
    AXI4 Multi Port Bridge for Memory Controller IP Core
  • MIPI CSI-2 to HDMI Reference Design

    Reference Design

    MIPI CSI-2 to HDMI Reference Design

    MIPI CSI-2 to HDMI Reference Design includes the synthesizable MIPI-HDMI core design & stimulus generators, checkers, & a testbench necessary to simulate the design
    MIPI CSI-2 to HDMI Reference Design
  • CSI-2/DSI D-PHY Transmitter IP Core

    IP Core

    CSI-2/DSI D-PHY Transmitter IP Core

    The CSI-2/DSI D-PHY Transmitter Submodule IP is for applications requiring D-PHY transmitter in the FPGA logic & supports both high-speed & low power modes
    CSI-2/DSI D-PHY Transmitter IP Core
  • FPD-LINK Transmitter IP Core

    IP Core

    FPD-LINK Transmitter IP Core

    The FPD-LINK Transmitter Interface IP translates DSI video streams to LVDS interface for an FDP-Link connection to displays.
    FPD-LINK Transmitter IP Core
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