​​Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design​

​​Bridging Processor with a MIPI DSI and MIPI CSI-2 Interface​

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​​The Lattice Semiconductor MIPI-to-Parallel and Parallel-to-MIPI reference design allows the quick interface for a processor with a MIPI DSI interface to or from a display with an RGB interface, or a camera with a MIPI CSI-2 interface to or from a processor with parallel interface. This reference design provides the conversion for Lattice Avant™ devices and is useful for wearable, tablet, human machine interfacing, medical equipment, and many other applications.​

Features

  • ​​Compliant with MIPI D-PHY v1.2 and MIPI CSI-2 v1.2 specifications
  • Supports MIPI D-PHY interfacing from 160 Mb/s up to 800 Mb/s
  • Supports 1, 2, or 4 data lanes and one clock lane
  • Supports continuous and non-continuous MIPI D-PHY clock
  • Supports common MIPI CSI-2 compatible video formats (RGB888, RAW8, RAW10, RAW12, RAW14, RAW16, YUV_420_8, YUV_420_10, YUV_422_8, YUV_422_10)​

Block Diagram

​​Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design​ Block DiagramExpand Image

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design – User Guide​
FPGA-RD-02287 1.0 6/14/2024 PDF 3.3 MB
Lattice Avant MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design – Source Code​
1.0 6/14/2024 ZIP 15.7 MB

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