XIP3032H: SHA3-256

High-speed IP core implementing the SHA-3 (FIPS PUB 202) with a 256 bit message digest

Related Products

XIP3032H calculates a message digest (also commonly known as a hash value) with a length 256 bits, and pads pads the incoming message into 1088 bits long message blocks as specified in FIPS PUB 202.

The hash computing engine of XIP3032H is based on the hardware-friendly Keccak sponge algorithm.

Easy integration with other FPGA logic, as the functionality of XIP3032H does not rely on any FPGA family specific features.

Features

  • Modest Resource Requirements: The entire XIP3032H requires 7160 4LUTs (Lookup Tables), and does not require any multipliers, DSPBlocks or internal memory in a typical FPGA implementation.
  • Performance: Despite its modest size, XIP3032H achieves a throughput in the Gbps range, for example 3.22+ Gbps in Lattice ECP5.
  • Standard Compliance: XIP3032H is fully compliant with the Secure Hash Algorithm-3 FIPS PUB 202.

Block Diagram

Internal high-level block diagram of XIP3032HExpand Image

Resource Usage and Performance

FPGA family Resources fMAX Max. Throughput
Lattice ECP5 7160 4LUTs 78.01 MHz 3.22 Gbps

Resource usage and performance of XIP3032H on Lattice ECP5 FPGA family. On request, the resource estimates can also be supplied for other Lattice FPGA families.

Ordering Information

Please contact sales@xiphera.com for pricing and your preferred delivery method. XIP3032H can be shipped in a number of formats, including netlist, source code, or encrypted source code. Additionally, a comprehensive VHDL testbench and a detailed datasheet are included.

You can download the Lattice Product Brief from https://xiphera.com/partners/lattice/XIP3032H_PB_lattice.pdf

Documentation

Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Xiphera Lattice IP Core Metrics
1.0 8/5/2021 PDF 41.2 KB

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