XIP3026B: SHA512, SHA384, SHA512/256 and SHA512/224

Balanced IP core implementing SHA512, SHA384, SHA512/216 and SHA512/224 as specified in FIPS PUB 180-4

XIP3026B calculates a message digest (also commonly known as a hash value) with a length of either 512 bits (SHA512), 384 bits (SHA384), 256 bits (SHA512/256), or 224 bits (SHA512/224).

XIP3026B pads and parses the incoming message into 1024 bits long message blocks as specified FIPS PUB 180-4, and adds the length information to the last 64 bits of the last 1024 bits long message block.

Easy integration with other FPGA logic, as the functionality of XIP3026B does not rely on any FPGA family specific features.


  • Compact resource requirements: The entire XIP3026B requires 4255 Lookup Tables (4LUTs) (Lattice ECP5), and does not require any multipliers, DSPBlocks or internal memory in a typical FPGA implementation.
  • Performance: Despite its compact size, XIP3026B achieves a high throughput, for example 0.60+ Gbps in Lattice ECP5.
  • Standard Compliance: XIP3026B is fully compliant with the Secure Hash Standard FIPS PUB 180-4 published by the National Institute of Standards and Technology (NIST).

Block Diagram

Resource Usage and Performance

FPGA family Resources fMAX Max. Throughput
Lattice ECP5 4255 4LUTs 48.76 MHz 0.60 Gbps

Resource usage and performance of XIP3026B on Lattice ECP5 FPGA family. On request, the resource estimates can also be supplied for other Lattice FPGA families.

Ordering Information

Please contact sales@xiphera.com for pricing and your preferred delivery method. XIP3026B can be shipped in a number of formats, including netlist, source code, or encrypted source code. Additionally, a comprehensive VHDL testbench and a detailed datasheet are included.

You can download the Lattice Product Brief from https://xiphera.com/partners/lattice/XIP3026B_PB_lattice.pdf


Information Resources
Xiphera Lattice IP Core Metrics
1.0 8/5/2021 PDF 41.2 KB
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