Balanced IP core implementing the MACsec protocol as standardized in IEEE Std 802.1AE-2018

XIP1211B uses Advanced Encryption Standard with 128 bits long key in Galois Counter Mode (AES-GCM) to protect data confidentiality, data integrity and data origin authentication.

Easy integration with other FPGA logic, as the functionality of XIP1211B does not rely on any FPGA family specific features.


  • Moderate resource requirements: The entire XIP1211B requires 23620 Lookup Tables (4LUTs) (Lattice ECP5), and does not require any multipliers or DSPBlocks in a typical FPGA implementation.
  • Performance: XIP1211B achieves a high throughput, for example 1.24+ Gbps in Lattice ECP5.
  • Standard Compliance: XIP1211B is fully compliant with the MACsec protocol as standardized in IEEE Std 802.1AE-2018.
  • The cipher suite (GCM-AES-128 or GCM- AES-XPN-128) is fully compliant with the Advanced Encryption Algorithm (AES) standard FIPS-197, as well as with the Galois Counter Mode (GCM) standard SP 800-30D.
  • Test Vector Compliance: XIP1211B passes the relevant test vectors specified in Annex C of IEEE Std 802.1AE-2018.

Block Diagram

Resource Usage and Performance

FPGA family Resources fMAX Max. Throughput
Lattice ECP5 23620 4LUTs, 34 EBR 96.57 MHz 1.24 Gbps

Resource usage and performance of XIP1211B on Lattice ECP5 FPGA family. On request, the resource estimates can also be supplied for other Lattice FPGA families.

Ordering Information

Please contact sales@xiphera.com for pricing and your preferred delivery method. XIP1211B can be shipped in a number of formats, including netlist, source code, or encrypted source code. Additionally, a comprehensive VHDL testbench and a detailed datasheet are included.

You can download the Lattice Product Brief from https://xiphera.com/partners/lattice/XIP1211B_PB_lattice.pdf


Information Resources
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Xiphera Lattice IP Core Metrics
1.0 8/5/2021 PDF 41.2 KB

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