eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

eUSB31SF IP core is designed using the Lattice® Semiconductor CL-NX FPGA built-in transceiver ensuring highest throughput i.e. >3.4Gbps

Related Products

FIFO Interface – To transfer data over non-zero endpoint, user just needs to manage this FIFO interface. User can write down VHDL, Verilog or System Verilog code to manage this FIFO interface.

Software managed control endpoint - In this IP core, processor is responsible to manage transfer for endpoint 0 (default control endpoint). IP core has AHB Lite interface by which processor can communicate with IP core. This provides flexibility to the user to manage enumeration data.

Application - This IP core is well suited when user recognizes that software is not required to process data to be passed over data endpoint.

Features

  • It supports SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes
  • Uses Lattice CL-NX FPGA Transceiver as a PHY layer and thus eliminates need for external PHY for USB 3.1
  • Provides ULPI interface to interact with external USB 2.0 PHY
  • Capable to support up to 31 endpoints (1 default control endpoint, 15 IN endpoints and 15 OUT endpoints)
  • Allows to select number of buffers per endpoint based on the requirement

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