xSPI Target (eXpanded Serial Peripheral Interface Target) IP Core

Configurable SPI/QSPI Target Controller for Embedded Peripherals

The Lattice xSPI Target IP is a flexible Serial Peripheral Interface (SPI) solution that supports both standard and quad SPI (QSPI) protocols. Designed for seamless integration in embedded systems, it enables reliable data transfer between microcontrollers and peripheral devices such as sensors, memory, and display controllers.

Standard SPI provides a legacy four-wire interface with dedicated input and output data lines, while QSPI extends this capability with four data lines for significantly higher data throughput. The xSPI Target IP accommodates both modes, giving designers the flexibility to optimize for compatibility or performance depending on their application requirements.

Features

  • Legacy SPI support
  • x1 and x4 I/O widths
  • Basic SPI write and SPI read
  • SPI clock frequencies up to 50 MHz
  • AMBA APB and AHB-Lite bus interface

Jump to

Block Diagram

Ordering Information

The xSPI Target IP is provided at no additional cost with the Lattice Radiant software.

Documentation

Quick Reference
Information Resources
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xSPI Target IP Core - Driver API Reference
FPGA-TN-02426 1.0 6/26/2026 PDF 695.4 KB
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xSPI Target IP Core - User Guide
FPGA-IPUG-02323 1.0 6/26/2026 PDF 1.3 MB
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xSPI Target IP Core - Release Notes
FPGA-RN-02115 1.0 6/26/2026 PDF 310.4 KB

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