Multi-Port Arbiter for DDR3 Memory Controller IP Core

Memory Controller for Video, Embedded and Communications Applications from many sources

The Multi-Port Arbiter for DDR3 Memory Controller IP Core features an arbiter and acts as a hub that connects multi-users with DDR3.

A Multi-Port Memory Controller (MPMC) is commonly used in many video, embedded, and communication applications where data from multiple sources moves through a common memory device, typically an LPDDRx or a DDRx SDRAM.

The Lattice Semiconductor Multi-Port AHB-Lite Arbiter for Memory Controller IP Core (MPMC_AHBL IP Core) provides multi-port capability to the existing Lattice Memory Controller IP Core. It allows up to eight independent AHB-Lite masters to access the Lattice Memory Controller IP Core, which has a single AHB-Lite interface. This IP core is fully compliant with AMBA 3 AHB-Lite Protocol v1.0.


  • Parameterized design that supports 1 to 8 user ports
  • Ports that can be independently configured to be a Read or Write port and individually be connected through the AHB-Lite interface
  • Two kinds of arbitration modes, Round-robin and Fixed priority
  • Configurable data width similar to the DDR3 data width
  • APB 1.0 interface support for control operations

Jump to

Block Diagram

Performance and Size

Resource Utilization using LIFCL-40-9BG400I
Configuration clk_i Fmax (MHz)1 ahb_clk_i Fmax (MHz)1 Registers LUTs EBRs DSPs
Default 200 200 1172 1825 1 0
Number of User Ports = 8, AHB Data width = 64, others = Default 200 169.895 2310 4539 1 0
Number of User Ports = 8, Arbitration Mode = Round Robin, AHB Data width = 64, others = Default 200 169.895 2312 4429 1 0

Ordering Information

The Multi-Port Arbiter for DDR Memory Controller is available for free to use in Lattice Radiant design software.


Quick Reference
Memory Modules - Lattice Radiant Software
FPGA-IPUG-02033 2.5 6/23/2021 PDF 2.4 MB
Multi Port Arbiter for DDR3 Memory Controller IP Core - Lattice Radiant Software
FPGA-IPUG-02132 1.0 6/23/2021 PDF 1.1 MB

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