Tiny Hash Core

Helion Tech LogoThe Helion Tiny Hash Core family for Lattice FPGA offers a combination of high functionality and low resource usage for lower data rate applications than the Helion Fast Hash Core family. The core is available in versions which support one or more of the five NIST approved cryptographic hashing algorithms described in FIPS 180-3; SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512, plus the legacy MD5 algorithm described in RFC 1321.

It can optionally support the standard Keyed Hash-based Message Authentication Code (HMAC) algorithm described in FIPS 198-1 which is widely used for data authentication and integrity checking in a number of data security protocols. Support for full hash state unload and reload also greatly improves system throughput when hashing interleaved or packetised message streams. A simple synchronous host system interface ensures easy connection into any end user application whether employed as a hardware hashing accelerator for an embedded processor, or connected directly into the datapath.

Features

  • Implements one or more of SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 & MD5 hash algorithms
  • Supports Keyed Hashing for Message Authentication (HMAC) to FIPS 198-1
  • Supports state unload/reload operations to optimise hashing of interleaved message streams
  • Highly optimised for use in Lattice FPGA technology
  • Provides high functionality for low resource in low data rate applications
  • Ideally suited for use as a hashing co-processor in embedded FPGA applications
  • Choice of 8 or 32-bit host system interface data bus width

Jump to

Block Diagram

Ordering Information

This IP core is supported and sold by Helion Technology, contact Helion Technology at info@heliontech.com or visit their website at www.heliontech.com for more information.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Helion Technology - Tiny Hash Core
3/23/2011 PDF 81.3 KB

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