Speed Sign Detection AI Demo

Lattice sensAI Demo

Speed Sign Detection demo uses the Convolutional Neural Network (CNN) for automotive applications. CNNs enables the traditional tasks typically performed by humans to improve a more efficient and faster implementation of data. Parallelization in FPGAs makes them most suited for implementing neural networks.

Convolutional Neural Network used in this demonstration can be trained by passing multiple traffic signs through the untrained model to calculate weights and activations. This creates a trained model of weights and activations read by the CNN Accelerator implemented in ECP5 FPGA. The end result is that the camera can detect and display the speed limits when the sign passes in front of it, displaying the indicated speed.

Low-power, production-priced ECP5 brings best in class power vs. performance efficiency in neural networks implemented. Such Edge implementation keeps processing local thus improving security.

Features

  • Accelerated, speed limit detection CNN implemented in low-power, production-priced ECP5
  • Configuration files provided for rapid implementation on Embedded Vision Development Kit
  • Uses weights and activations based on real speed limit signs maintaining high accuracy
  • The neural network is highly customizable and can be trained to detect speed signs from all over the world
  • Internal EBR blocks used to store activations, minimizing DRAM access
  • ECP5 is ready for automotive application with AEC-Q100 qualified devices
Lattice sensAI

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Video

Speed Sign Detection Using ECP5 and CNNs
Expand Video

Speed Sign Detection Using ECP5 and CNNs

  • This demonstration looks for speed limit signs and interprets what is on the sign
  • The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA
  • Power consumption is less than 1W

Block Diagram

Speed Limit Detection Block Diagram

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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EVDK Based Speed Sign Detection Demonstration User Guide
FPGA-UG-02049 1.2 6/28/2021 PDF 1.5 MB
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EVK Based Speed Sign Detection Demonstration Bitstreams
1.1 9/25/2018 ZIP 3.2 MB

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