MIPI CSI-2 to HDMI Demonstration

Demonstrable Design using MIPI Sensor and HDMI Monitor using Lattice IPs

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MIPI-HDMI Demonstration is built using multiple Lattice IPs and some additional glue logic necessary to connect the IPs in a processing pipeline. The Lattice IPs included in this design are: MIPI CSI-2 Receiver, Byte to pixel, Debayer, Automatic white balance (AWB) and Color correction matrix (CCM).

The MIPI CSI-2 to HDMI Demonstration includes the MIPI-HDMI Core Design and other glue logic necessary to interface with the hardware board and external devices, like clock synthesizer control, I2C controller for the sensor, I2C controller for HDMI, etc.

MIPI CSI-2 to HDMI Reference Design – The functioning of the full design is demonstratable live by using a MIPI sensor for video input and a HDMI monitor for displaying the output.

Features

  • The demo was run using the Avant-E Evaluation Board
  • Input comes through the Lattice DP FMC daughter card for MIPI sensor
  • A commercially available HDMI FMC daughter card is used for HDMI output

To learn more about this product design and request the complete source code, click here to contact us.

Block Diagram

MIPI CSI-2 to HDMI Reference Design Block DiagramExpand Image

MIPI-HDMI Core Design Block Diagram

MIPI CSI-2 to HDMI Demonstration Block DiagramExpand Image

MIPI CSI-2 to HDMI Demonstartion Block Diagram

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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MIPI CSI-2 to HDMI Reference Design - User Guide
FPGA-UG-02206 1.0 12/22/2023 PDF 2.3 MB
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MIPI CSI-2 to HDMI Demonstration - Bitstream
12/22/2023 ZIP 1.8 MB

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