Lattice Solutions

Everything you need to quickly and easily complete your design

Share This Result >

Narrow Your Results



Solution Type



Device Support
















Tags



































































































Providers









Clear All
  • PCIe Basic Demo on Crosslink-NX PCIe Bridge Board

    Demo

    PCIe Basic Demo on Crosslink-NX PCIe Bridge Board

    The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
    PCIe Basic Demo on Crosslink-NX PCIe Bridge Board
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo that displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • User Tracking and Onlooker Detection Demostration

    Demo

    User Tracking and Onlooker Detection Demostration

    Sample demonstration for detection and tracking of multiple human faces running on a low power general purpose FPGA using CNN Model
    User Tracking and Onlooker Detection Demostration
  • CrossLink-NX Voice and Vision Machine Learning Board

    Board

    CrossLink-NX Voice and Vision Machine Learning Board

    Designed for low-power machine learning applications with Lattice sensAI and CrossLink-NX. Includes image sensors, microphones, HyperRAM, and expansion ports.
    CrossLink-NX Voice and Vision Machine Learning Board
  • Timer/Counter IP Core

    IP Core

    Timer/Counter IP Core

    Timer/Counter IP used to track timeouts in the system. Target devices are Certus-NX and Crosslink-NX.
    Timer/Counter IP Core
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    Propel IP Module: 32-bit RISC-V processor core with optional Timer and PIC sub-modules, connects via AHB-Lite bus to other Propel IP modules and more.
    RISC-V MC CPU IP Core
  • CrossLink-NX 評価ボード

    Board

    CrossLink-NX 評価ボード

    CrossLink-NX 評価ボードは 40K ロジックセルのCrossLink-NXを搭載: ほとんどの I/O に簡単にアクセス可能、FPGA の PCIe 5G SERDES: FPGA メザニンカード (FMC)、Raspberry Pi、MIPI CSI-2、D-PHY、拡張用汎用ヘッダ
    CrossLink-NX 評価ボード
  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification Reference Design
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • Helion IONOS画像シグナル処理IPポートフォリオ

    IP Core

    Helion IONOS画像シグナル処理IPポートフォリオ

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS画像シグナル処理IPポートフォリオ
  • CSI-2 / DSI D-PHY レシーバ

    IP Core

    CSI-2 / DSI D-PHY レシーバ

    MIPI D-PHY はカメラやディスプレイの標準的なインタフェースです。この IP を使用すると FPGA に D-PHY レシーバを実装できます。
    CSI-2 / DSI D-PHY レシーバ
  • FPD-Link トランスミッタ

    IP Core

    FPD-Link トランスミッタ

    OpenLDI / FPD-Link / LVDS トランスミッタ・インタフェース IP は ピクセルデータフォーマットのビデオデータを FPD-Link やその他の LVDS ディスプレイインタフェースへ変換します。
    FPD-Link トランスミッタ
  • FPD-Link レシーバ

    IP Core

    FPD-Link レシーバ

    OpenLDI / FPD-Link / LVDS レシーバ・インタフェース IP はプロセッサからの OpenLDI / FPD-Link / LVDS 入力をピクセルクロックドメインへ変換します。この IP は他の IP 組み合わせて MIPI DSI ディスプレイインタフェース変換として使用されます。
    FPD-Link レシーバ
  • SubLVDS イメージセンサーレシーバ

    IP Core

    SubLVDS イメージセンサーレシーバ

    MIPI D-PHY モジュラー IP - SubLVDS イメージセンサビデオデータをピクセルクロックドメインに変換
    SubLVDS イメージセンサーレシーバ
  • Page 1 of 7
    First Previous
    1 2 3 4 5 6 7
    Next Last
    Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.