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  • CrossLinkU-NX Evaluation Board

    Board

    CrossLinkU-NX Evaluation Board

    CrossLinkU-NX Evaluation Board is a platform for general purpose application development using CrossLinkU-NX device, the first FPGA with hard USB2/3 (5Gbps) interface.
    CrossLinkU-NX Evaluation Board
  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    USB 2.0/3.2 IP Core
  • USB to I/O Aggregation and Bridging Demonstration

    Demo

    USB to I/O Aggregation and Bridging Demonstration

    The USB to I/O Aggregation and Bridging Demo shows the capabilities of the Lattice FPGA and accelerating USB 2.0/3.2 (5Gbps) Interface Innovation.
    USB to I/O Aggregation and Bridging Demonstration
  • USB to I/O Aggregation and Bridging Reference Design

    Reference Design

    USB to I/O Aggregation and Bridging Reference Design

    USB to IO Bridging Reference Design Create plug-and-play peripheral expansion on USB-enabled FPGA & signal protocol conversion from USB to I2C, SPI, & GPIO.
    USB to I/O Aggregation and Bridging Reference Design
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
    Object Classification Reference Design
  • PCIe Basic Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Basic Demo for Lattice Nexus-based FPGAs

    The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
    PCIe Basic Demo for Lattice Nexus-based FPGAs
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • User Tracking and Onlooker Detection Demonstration

    Demo

    User Tracking and Onlooker Detection Demonstration

    Sample demonstration for detection and tracking of multiple human faces running on a low power general purpose FPGA using CNN Model
    User Tracking and Onlooker Detection Demonstration
  • CrossLink-NX Voice and Vision Machine Learning Board

    Board

    CrossLink-NX Voice and Vision Machine Learning Board

    Designed for low-power machine learning applications with Lattice sensAI and CrossLink-NX. Includes image sensors, microphones, HyperRAM, and expansion ports.
    CrossLink-NX Voice and Vision Machine Learning Board
  • CrossLink-NX-33 Voice and Vision Machine Learning Board

    Board

    CrossLink-NX-33 Voice and Vision Machine Learning Board

    CrossLink-NX-33 Voice and Vision Machine Learning Board is designed using Crosslink-NX 33K, ideal for machine learning applications.
    CrossLink-NX-33 Voice and Vision Machine Learning Board
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • CrossLink-NX 評価ボード

    Board

    CrossLink-NX 評価ボード

    CrossLink-NX 評価ボードは 40K ロジックセルのCrossLink-NXを搭載: ほとんどの I/O に簡単にアクセス可能、FPGA の PCIe 5G SERDES: FPGA メザニンカード (FMC)、Raspberry Pi、MIPI CSI-2、D-PHY、拡張用汎用ヘッダ
    CrossLink-NX 評価ボード
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
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