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  • ​​JESD204B IP Core​

    IP Core

    ​​JESD204B IP Core​

    ​​The Lattice JESD204B IP Core is a high-speed serial interface used between data converters, and the FPGA device to replace traditional interfaces.​
    ​​JESD204B IP Core​
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • DDR3 Memory Interface Demonstration

    Demo

    DDR3 Memory Interface Demonstration

    The Lattice DDR3 Memory Interface demonstrates the functionality of DDR3 SDRAM Controller IP at core speed of 400MHz and 800Mbps.
    DDR3 Memory Interface Demonstration
  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification Reference Design
  • Helion IONOS画像シグナル処理IPポートフォリオ

    IP Core

    Helion IONOS画像シグナル処理IPポートフォリオ

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS画像シグナル処理IPポートフォリオ
  • Lattice Image Signal Processing Demo

    Demo

    Lattice Image Signal Processing Demo

    Provides a complete ISP example design on the Lattice ECP5 FPGA for the Embedded Vision Development Kit, ideal for Industrial, Medical, and Automotive applications.
    Lattice Image Signal Processing Demo
  • Lattice Image Signal Processing Reference Design

    Reference Design

    Lattice Image Signal Processing Reference Design

    Configure an ECP5 FPGA-based ISP solution tailored to your Industrial, Medical, and Automotive application.
    Lattice Image Signal Processing Reference Design
  • 人感検出

    Demo

    人感検出

    Uses an artificial intelligence (AI) algorithm to detect human presence with either the powerful ECP5 FPGA, or small, low-power iCE40 UltraPlus FPGA.
    人感検出
  • 人数カウント

    Demo

    人数カウント

    人数カウントのデモはラティスのECP5 FPGAと畳み込みニューラルネットワーク(CNN)アクセラレーションエンジンを活用
    人数カウント
  • 荷物検出

    Demo

    荷物検出

    LatticeECP5 FPGA組込みビジョン開発キットに実装されたYOLO CNNを使用した荷物(小包)検出デモ
    荷物検出
  • 車両の識別

    Demo

    車両の識別

    LatticeECP5 FPGA組込みビジョン開発キットに実装されたYOLO CNNを使用した荷物(小包)検出デモ
    車両の識別
  • 速度標識検出

    Demo

    速度標識検出

    Lattice sensAI スタックを使った速度標識検出
    速度標識検出
  • LimeSDR Mini Development Board by Lime Microsystems

    Board

    LimeSDR Mini Development Board by Lime Microsystems

    LimeSDR Mini Dev Board is a low cost, open source and apps-enabled SDR platform that can be used to support any type of wireless communication standard.
    LimeSDR Mini Development Board by Lime Microsystems
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