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Article Details

ID: 5435
Case Type: faq
Category: Lattice IP/Reference Design
Related To: DDR3 SDRAM Controller
Family: LatticeECP5

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What is the "TRC_DQS*" in DDR3 SDRAM Controller IP?

All the TRC_DQS parameters below are for write leveling mode and used only for the simulation.


Referring to DDR3 DIMM memory model in the generated core package, users can find these parameters to provide fly by wiring modeling for simulation. If the user selected the write leveling mode, the parameters will have different values to model the fly by wiring. Otherwise, users should be the same value. It is only for simulation to support Write Leveling and should not affect the HW behavior unless you make a change on Write leveling setting.
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