I have a 3-stage shift register, the software always implement it in a dual-port RAM, how can I avoid the RAM-based shift register?
Here is the original Verilog code:
reg [6:0] shft_reg1, shft_reg2, shft_reg3;
always @(posedge pclk) begin
shft_reg1 <= din;
shft_reg2 <= shft_reg1;
shft_reg3 <= shft_reg2;
end
I would like to keep those shift components as registers.
Solution 1:
The Synthesis tool will determine whether to implement the sequential shift register as register, distribute-RAM or block RAM based on certain criteria. The user can choose a different implementation by specifying syn_ramstyle or syn_srlstyle attributes. The attributes can be applied globally, to a module or to a RAM instance. For examples:
module (...) /* synthesis syn_ramstyle="block_ram" */;
or
reg [3:0] regBank[15:0] /* synthesis syn_srlstyle="registers" */;
For more details of the Syntax and attribute value, please refer to the online help Synplify reference manual.
Solution 2:
An alternative solution is to use syn_keep attribute to preserve those register signals. The Synplify will automatically implement the shift component as registers.