DC-SCM 2.0 LVDS Tunneling Protocol & Interface (LTPI) Block Diagram
LVDS Tunneling Protocol & Interface (LTPI) Reference Design Walkthrough Guide
LVDS Tunneling Protocol & Interface (LTPI) IP Walkthrough
Virtual Laboratory for Remote Demonstration
Dual Host Processor Module (HPM) and Single Secure Control Module (SCM) Proof of Concept Demo
Device Attestation over LVDS Tunneling Protocol & Interface Specification (LTPI)
Intel Lincoln City Reference Architecture with Lattice FPGAs
Lattice eSPI Target IP Core is compliant with the Intel eSPI specifications & has its own virtual wire channel in the user interface.
The Lattice M-PESTI IP core provides early peripheral presence detection and attribute collection before system boot up.
LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
This is a CPLD design template for the Secure Control Module (SCM) and Host Platform Module (HPM) for the Sentry 4.0 Server solution platform.
SCM,
HPM,
CPLD,
Lattice Sentry,
Security,
Defense,
LTPI,
MPESTI,
SGPIO,
eSPI,
OCP The design specifically targets MIPI CSI-2 camera sensors and offers a flexible architecture capable of integrating multiple camera inputs based on system requirements.
The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
CRC,
LVDS,
I2C,
GPIO,
UART,
LTPI,
AMBA,
APB,
Lattice Diamond,
Lattice Propel,
OCP Quick Reference | Technical Resources |
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