The high-speed MACsec IP core from Xiphera implements the MACsec protocol as standardized in IEEE Std 802.1AE-2018. The MACsec protocol defines a security infrastructure for Layer 2 (as per the OSI model) traffic by assuring that a received frame has been sent by a transmitting station that claimed to send it. The IP core uses Advanced Encryption Standard with 256 bits long key in Galois Counter Mode (AES-GCM) to protect data confidentiality, data integrity, and data origin authentication.
Performance: The balanced MACsec IP core achieves a high throughput, for example 889.03+ Gbps in Lattice CertusPro-NX.
Standard Compliance: The IP core is fully compliant with the MACsec protocol as standardised in IEEE Std 802.1AE-2018. The cipher suite (GCM-AES-256 or GCM-AES-XPN-256) is fully compliant with the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard.
Moderate Resource Requirements: The entire IP core requires 23967 4-input Lookup Tables (4LUTs) (Lattice CertusPro-NX), and does not require any multipliers or DSPBlocks in a typical Lattice® FPGA implementation.