The Flash Access IP core for MachXO5™-NX devices enables you to perform write and read access to the internal flash memory of LFMXO5-25, LFMXO5-55T, and LFMXO5-100T devices. The write and read access are performed through the LMMI interface.
Resource Utilization details are available in the IP Core User Guide.
Features
- Supports LMMI interface.
- Supports initial user data to be programmed into the flash memory.
- Supports up to 50 MHz input clock frequency.
- Optional LMMI interface for configuration access.
- This is only supported in LFMXO5-25, LFMXO5-55T, and LFMXO5-100T devices.
