APB Interconnect Module

Interconnect fabric for AMBA 3 APB based systems

The Lattice Semiconductor APB Interconnect Module is a fully parameterized soft IP for low latency interconnect fabric for APB system. It can be used to connect one or more APB bus master to one or more APB bus slave. Master-side arbitration is implemented within the module to minimize resource utilization.

The APB Interconnect Module supports round-robin based and fixed priority-based arbitration when multiple bus masters access the same slave port. The arbitration completes in one clock cycle, which means that the transaction is delayed by one clock cycle when arbitration occurs.

The design is implemented in Verilog HDL. The IP can be configured and generated using Lattice Propel Builder software. It can be targeted to MachXO3D FPGA devices and implemented using the Lattice Diamond software Place and Route tool integrated with the Synplify Pro synthesis tool.


  • Compliance with AMBA 3 APB Protocol v1.0
  • Data Bus width of up to 32 bits [8, 16, 32]
  • Address width of up to 32 bits [11,12,...,32]
  • Support to up to 32 masters and 32 slaves
  • Slave port address decoding
  • Master side arbitration
Lattice Propel

Block Diagrams

APB Interconnect Module Block Diagram


Quick Reference
Select All
APB Interconnect Module - Lattice Propel Builder
FPGA-IPG-02054 1.2 5/11/2021 PDF 887.6 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.