Enabling connectivity in HetNet systems

JESD207 is a Radio Front End – Base Band Digital Parallel (RBDP) interface between a Radio Front-end integrated circuit (RFIC) and a Baseband integrated circuit (BBIC). This IP core together with DDR and PLL functionality integrated in the LatticeECP3™ FPGAs implements baseband (BB) side data and control plane paths. It can be used to connect to a radio front-end (RF) transceiver device with integrated analog to digital converter (ADC) and digital to analog converter (DAC).

JESD207 IP Diagram

The Lattice JESD207 IP core is fully compliant to the JESD207 JEDEC specification.


Data Path Feature

  • Data path clock and data rate controlled by RFIC (configured by BBIC) up to 90 MHz and 180 MSps
  • Data width matched to baseband sample width – 10 or 12 bits
  • Raw data path interface transfer bandwidth up to 1.8 or 2.2 Gbps
  • Double data rate (DDR) source-synchronous data path transfer timing
  • Low latency (single baseband complex sample period) data transfer

  • Low implementation complexity

Control Plane Path Feature

  • Clock rate and serial transfer rate controlled by BBIC up to 50 MHz
  • 1-bit command + 7-bit address control field format
  • Flexible transaction format using one or more 8-bit data fields per transaction to allow per-transaction optimization of latency or bandwidth – minimum 325ns transaction latency with 8-bit data transactions (maximum 24 Mbps data rate) – data rates above 40 Mbps can be achieved with extended transactions
  • Serial clock can be stopped between transactions, reducing control plane power consumption to negligible levels.

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Block Diagram

JESD207 IP Block Diagram


Quick Reference
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JESD207 IP Core User's Guide
IPUG111 1.0 8/27/2013 PDF 2.4 MB

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