The 2D Scaler IP core converts input video frames of one size to output video frames of a different size. Its flexible architecture supports a wide variety of scaling algorithms. The highly configurable design takes advantage of the embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either streaming video or bursty input video data. In-system input and output frame size update is possible on a frame basis.