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    ID
    Family
    Category
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  • iCE40: How to identify true (positive) and complementary (negative) ball functions for Low Voltage…
    3862
    iCE40
    Inquiries
    Appnote/Technote
  • Are Lattice IP (Intellectual Property) reset signals connected to the GSR (Global Set/Reset) modules…
    3843
    All FPGA
    Lattice IP/Reference Design
    All
  • Diamond: How to create a VHDL output from a schematic file?
    3845
    MachXO2
    Entry
    Schematic
  • Lattice Mico: Do iCE devices support LatticeMico8/LatticeMico32 Soft-Processor?
    3882
    iCE40
    Implementation
    Mico32(MSB)
  • LatticeXP2: How to do background programming of external SPI flash connected to XP2?
    3887
    LatticeXP2
    Device Programming
    Configuration/Programming
  • iCE40: Is it possible with the signal 'ENABLE_OUTPUT' of the primitive SB_IO to create a…
    3881
    iCE40
    Architecture
    IO
  • [MachXO2/PLL]: How to perform dynamic changes to the PLL output frequency?
    3815
    MachXO2
    Architecture
    PLL/DLL/Clock Routing
  • What is the differencebetween solder ball diameter and solder ball land diameter in TN1074, PCB…
    3813
    All FPGA
    Customer Board Design
    Layout
  • LatticeECP3: Does Lattice have a reference design to support Reduced Gigabit Media Independent…
    3819
    LatticeECP3
    Lattice IP/Reference Design
    RGMII to GMII Bridge
  • LatticeXP2: Is the download/configuration time from Internal/External SPI Flash different while…
    3817
    LatticeXP2
    Device Programming
    Configuration/Programming
  • How to find the number of gates available for a Lattice device?
    3812
    LatticeXP2
    Inquiries
    Datasheet
  • Diamond / Implementation: How to have consistent bus signal names while switching between Synplify…
    3816
    All FPGA
    Implementation
    LSE (Lattice Synthesis Engine)
  • Which development tool/software should be used to implement a design on ispLSI3320 device?
    3811
    ispLSI2000
  • For the MachXO2 EFB (Embedded Functional Block) I2C, when is the TRRDY (Transmit Ready) bit of the…
    3778
    MachXO2
    Architecture
    Embedded Functional Block (EFB)
  • Diamond / Spreadsheet View: How are the allowance and the percentage related in the Lattice Diamond…
    3772
    MachXO2
    Implementation
    SSO Analysis
  • Diamond: How to use the IEEE_PROPOSED library in my VHDLcode in Synplify Pro?
    3782
    All FPGA
    Entry
    Synopsys
  • Internal Reference: For the MachXO2 EFB (Embedded Functional Block), the Primary I2C cannot be used…
    3785
    MachXO2
    Architecture
    I2C
  • MachXO2: How to update the Configuration Flash of the MachXO2 in transparent mode using the svf file…
    3766
    MachXO2
    Device Programming
    Deployment Tool
  • Distributed_SPRAM: What is the limit of writing or reading of Single Port RAM for MachXO2 devices?…
    3767
    MachXO2
    Architecture
    Memory EBR/Distributed
  • Programmer: How to reduce the TCK frequency on JTAG port while configuring a device through TCL…
    3760
    Other FPGA
    Device Programming
    Cables
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