Answer Database

Have a question? We've got the answer.

Our system is going under maintenance starting September 22, 2023 at 8 PM Pacific and ending September 24, 2023 at 2:00 PM Pacific. During this window, the website may not be reachable. For immediate assistance, please contact techsupport@latticesemi.com.

Narrow Your Results


Search within results

Family
Category
Type of Issue
Related To
  • Topic
    ID
    Family
    Category
    Related To
  • How to solve the issue of "ispVM System  doesn't detect  parallel port ISP Download Cable" ?
    209
    All FPGA
    Device Programming
    ispVM System
  • What is the initial logic level of a register after power-up?
    204
    All FPGA
    Architecture
    General Logic
  • I am having installation problems with ispLEVER Starter.
    208
    All Devices
    Installation
    Win-All
  • What are the required locations for the 7:1 LVDS pins on the LatticeXP2, LatticeECP2/M or…
    203
    All FPGA
    Customer Board Design
    Layout Review
  • How do I get a reasonable I/O timing report when PLL phase shift is very large?
    200
    All FPGA
    Implementation
    Timing Analysis
  • How can I configure the DDR3 memory clock to double the reference frequency (1:2:1 ratio) instead of…
    2087
    LatticeECP3
    Lattice IP/Reference Design
    DDR3 SDRAM Controller
  • What is the behavior of the Platform Manager Analog inputs? Is the voltage comparator output a logic…
    2085
    Platform Manager
    PAC-Designer
    LogiBuilder
  • Do Lattice devices contain any Rare Earth materials as mandated by the US Department of Commerce…
    2089
    All Devices
    Reliability and Materials
    Device Materials
  • How do I check the coverage of my timing constraints?
    2083
    All FPGA
    Implementation
    Timing Closure
  • How to effectively use secondary region clock in LatticeECP3 devices?
    2082
    LatticeECP3
    Architecture
    PLL/DLL/Clock Routing
  • Where can I find the driver for Lattice USB programming cable in Lattice Diamond ?
    2081
    All FPGA
    Device Programming
    Cables
  • How to check the un-constrained connections in Lattice Diamond?
    2084
    All FPGA
    Implementation
    Timing Closure
  • Can the POWR1220AT8 be used to monitor negative voltages?
    2040
    Power Manager II
    Architecture
    IO
  • Does ispVM Embedded support TAG memory operations with the XP2?
    2049
    LatticeXP2
    Device Programming
    ispVM Embedded
  • Can the CSSPIN pin be used as a GPIO in dual-boot mode on the LatticeXP2 device?
    2043
    LatticeXP2
    Architecture
    Configuration/Programming
  • How do I place DDR3 interface pins to minimize SSO impact?
    2041
    LatticeECP3
    Lattice IP/Reference Design
    DDR3 SDRAM Controller
  • I have 75 5V inputs to an ispMACH4000 device. Which I/O type should I use between LVTTL or LVTTL_5V?…
    2045
    ispMACH 4000
    Architecture
    IO
  • How much undershoot on the SDA pin can a POWR1220AT8 device endure without causing damaging?
    2038
    Power Manager II
    Architecture
    I2C
  • What are the last four characters in the JEDEC file of a Lattice CPLD ?
    2037
    All CPLD
    Device Programming
    Configuration/Programming
  • Using the command line, is there a command to directly convert .JED to .VME?
    2034
    All Devices
    Device Programming
    ispVM System
    • Page 1 of 125
    First Previous
    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
    		Next Last

    ABOUT LATTICE

    SALES

    SUPPORT

    FOLLOW