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    ID
    Family
    Category
    Related To
  • Lattice Radiant v2023.2: How to modify I2C slave address or 96-feabits using Pseudo mode?
    7336
    CertusPro-NX
    Programming and Configuration
  • Diamond/Radiant: How to disable GSR in Lattice Diamond/Radiant?
    7331
    All Devices
    Fabric
  • What type of pull ups are required for JTAG signals?
    791
    All ispClock
    Device Programming
    Cables
  • PLL: If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low…
    793
    LatticeECP2/M
    Architecture
    PLL/DLL/Clock Routing
  • iCEcube2: Can iCE40UP5k support tristates?
    5398
    iCE40 UltraPlus
    Implementation
    Synthesis
  • Where can I find the document for volatility for the USB programming cable?
    5307
    All Devices
    Device Programming
    Cables
  • All Devices: Can we access any NON-JTAG port (Wishbone, I2C, SPI or CPU) while SED is running in…
    5304
    MACHXO3
    Architecture
    Soft Error Detection (SED)
  • ispMACH4000: How to define "block-level initialization term" in Verilog?
    5303
    ispMACH 4000
    Entry
  • What is the difference between QFN32 described in the package diagrams document…
    5302
    MachXO2
    Inquiries
    Appnote/Technote
  • Does Lattice provide an RTL model of the L-ASC10 device to be used for simulation?
    5383
    MachXO2
    QuestaSim/Modelsim
    Closed-loop Trim/Fault Logger
  • CrossLink: Why does the generated VHDL code does not contain any ports for CSI2/DSI D-Phy Receiver…
    5389
    CrossLink
    MIPI D-PHY RX/TX
  • MachXO3LF: How do you generate internal Vref generator in the device?
    5368
    MACHXO3
    Implementation
  • Diamond / Programmer / MachXO2: How do you communicate with MachXO2 via SSPI when it is in user…
    5371
    MachXO2
    Device Programming
  • Can I set ODCLK frequency lower than recommended minimum frequency?
    5342
    Other Mixed Signal
    Inquiries
    Appnote/Technote
  • MACHXO3: How to configure the MachXO3LF device through I2C?
    5345
    MACHXO3
    Device Programming
  • All FPGA: Does Non-JTAG TransFR support I/O release during TranFR?
    5335
    MACHXO3
    Architecture
    Configuration/Programming
  • Diamond Programmer: Does Diamond Programmer software have versions that support 32-bit Windows?
    5330
    MachXO2
    Device Programming
    Diamond Programmer
  • LatticeECP2/M / LatticeECP3 / LatticeSC/M: What is the recommended connection for the XRES pin for…
    538
    All FPGA
    Customer Board Design
    Schematic Review
  • MachXO: Why can't I scan or program the MachXO device on the MachXO Mini board after I programmed my…
    534
    MachXO
    Device Programming
    Lattice Evaluation Boards
  • Why can't I drive a long PCB trace with a low current setting and get good signal quality?
    508
    All FPGA
    Customer Board Design
    Board Debug
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