Lattice Solutions

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  • Embedded Vision Development Kit

    Board

    Embedded Vision Development Kit

    Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
    Embedded Vision Development Kit
  • CrossLink-NX VIP Sensor Input Board

    Board

    CrossLink-NX VIP Sensor Input Board

    Intended for use with the Lattice Embedded Vision Development Kit. Includes 4 camera inputs and HyperRam for embedded video applications with CrossLink-NX
    CrossLink-NX VIP Sensor Input Board
  • CrossLink-NX Evaluation Board

    Board

    CrossLink-NX Evaluation Board

    For general evaluation and development with CrossLink-NX, includes many flexible interfaces such as FMC and PMOD with generous device IO access
    CrossLink-NX Evaluation Board
  • USB3-GbE VIP IO Board

    Board

    USB3-GbE VIP IO Board

    Output board for Video Interface Platform (VIP) and Embedded Vision Development Kit - adds video over USB 3.0 and Gigabit Ethernet.
    USB3-GbE VIP IO Board
  • Object Counting

    Reference Design

    Object Counting

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • Byte to Pixel Converter

    IP Core

    Byte to Pixel Converter

    Modular MIPI/D-PHY IP - Converts Parallel Data From a D-PHY Receiver into Pixel Format
    Byte to Pixel Converter
  • CSI-2/DSI D-PHY Receiver

    IP Core

    CSI-2/DSI D-PHY Receiver

    Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Receiver
  • CSI-2/DSI D-PHY Transmitter

    IP Core

    CSI-2/DSI D-PHY Transmitter

    Modular MIPI/D-PHY IP - PHY for transmitting MIPI CSI-2/DSI Data. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Transmitter
  • FPD-LINK Receiver

    IP Core

    FPD-LINK Receiver

    Modular MIPI/D-PHY IP - Converts FPD-LINK Video Streams to Pixel Clock Domain
    FPD-LINK Receiver
  • FPD-LINK Transmitter

    IP Core

    FPD-LINK Transmitter

    Modular MIPI/D-PHY IP - Convert Pixel Data Streams to an FPD-LINK Video Stream
    FPD-LINK Transmitter
  • Pixel to Byte Converter

    IP Core

    Pixel to Byte Converter

    Modular MIPI/D-PHY IP - Converts Pixel Format Data to Parallel Byte Format
    Pixel to Byte Converter
  • SubLVDS Image Sensor Receiver

    IP Core

    SubLVDS Image Sensor Receiver

    Modular MIPI/D-PHY IP - Converts SubLVDS Image Sensor Video Stream to Pixel Clock Domain
    SubLVDS Image Sensor Receiver
  • 1 to N MIPI CSI-2/DSI Duplicator

    Reference Design

    1 to N MIPI CSI-2/DSI Duplicator

    Modular MIPI/D-PHY Reference Design - Duplicate one MIPI CSI-2 channel to N DSI channels
    1 to N MIPI CSI-2/DSI Duplicator
  • 4 to 1 Image Aggregation with CrossLink-NX

    Reference Design

    4 to 1 Image Aggregation with CrossLink-NX

    Modular MIPI/D-PHY Reference Design - Aggregates four MIPI CSI-2 inputs to a single output stream.
    4 to 1 Image Aggregation with CrossLink-NX
  • MIPI CSI-2 Virtual Channel Aggregation

    Reference Design

    MIPI CSI-2 Virtual Channel Aggregation

    Modular MIPI/D-PHY Reference Design - Adaptable and flexible solution combines multiple MIPI CSI-2 inputs to a single CSI-2 output stream.
    MIPI CSI-2 Virtual Channel Aggregation
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
  • N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Reference Design

    N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Modular MIPI/D-PHY Reference Design - Aggregate multiple MIPI CSI-2 inputs up to 5 channels horizontally line by line to a single CSI-2 output
    N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation
  • SubLVDS to MIPI CSI-2 Image Sensor Bridge

    Reference Design

    SubLVDS to MIPI CSI-2 Image Sensor Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Pixel to Byte Converter, SubLVDS Image Sensor Recevier and CSI-2/DSI D-PHY Transmitter
    SubLVDS to MIPI CSI-2 Image Sensor Bridge
  • 4 Input to 1 Output MIPI CSI-2 Image Aggregation Demo

    Demo

    4 Input to 1 Output MIPI CSI-2 Image Aggregation Demo

    Modular MIPI/D-PHY Demonstration - Aggregates four MIPI CSI-2 inputs to a single parallel output stream, which is then displayed on HDMI.
    4 Input to 1 Output MIPI CSI-2 Image Aggregation Demo
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