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  • Embedded Vision Development Kit

    Board

    Embedded Vision Development Kit

    Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
    CrossLink, ECP5 / ECP5-5G 
    3D Video, Camera, DDR SDRAM, HDMI, Image Processing, Machine Learning/AI, Lattice sensAI, Signal Aggregation, Video Tx/Rx, VIP, Lattice mVision, IoT & Wearables, Smart Toys & Robots, Home Control Appliances & Security, Notebooks & PCs, Tablets, Printers, AR / VR & Drones, UAVs 
    Embedded Vision Development Kit
  • DDR3 Memory Interface Demonstration

    Demo

    DDR3 Memory Interface Demonstration

    The Lattice DDR3 Memory Interface demonstrates the functionality of DDR3 SDRAM Controller IP at core speed of 400MHz and 800Mbps.
    Certus-NX, ECP5 / ECP5-5G 
    DDR SDRAM 
    DDR3 Memory Interface Demonstration
  • USB3-GbE VIP IO Board

    Board

    USB3-GbE VIP IO Board

    Output board for Video Interface Platform (VIP) and Embedded Vision Development Kit - adds video over USB 3.0 and Gigabit Ethernet.
    CrossLink, ECP5 / ECP5-5G 
    Ethernet, USB3, Video Tx/Rx, VIP, Lattice mVision, Defense 
    USB3-GbE VIP IO Board
  • ECP5 Evaluation Board

    Board

    ECP5 Evaluation Board

    Evaluation and development for ECP5-5G FPGA - 85K LUTs. Includes generous IO access and easy expansion to PMOD, Arduino, RaspberryPI, SERDES interface and more
    ECP5 / ECP5-5G 
    Arduino, Breakout, PMOD, Raspberry Pi, SERDES, Versa Connector, TOR Switch, AR / VR & Drones, Defense 
    ECP5 Evaluation Board
  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    ECP5 / ECP5-5G, CertusPro-NX, CrossLink-NX 
    Object Detection, Object Identification, Lattice sensAI, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, UAVs 
    Human Face Identification Reference Design
  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    ECP5 / ECP5-5G, CrossLink-NX 
    Machine Learning/AI, Lattice sensAI, Object Counting, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, Automotive 
    Object Counting AI
  • Convolutional Neural Network (CNN) Accelerator IP

    IP Core

    Convolutional Neural Network (CNN) Accelerator IP

    Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    ECP5 / ECP5-5G 
    Machine Learning/AI, Lattice sensAI, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense 
    Convolutional Neural Network (CNN) Accelerator IP
  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    MachXO, LatticeXP2, LatticeECP3, CrossLink, ECP5 / ECP5-5G, CrossLink-NX 
    HDR, Image Processing, Video Tx/Rx, Lattice mVision, Automotive 
    Helion IONOS Image Signal Processing IP Portfolio
  • Lattice Image Signal Processing Demo

    Demo

    Lattice Image Signal Processing Demo

    Provides a complete ISP example design on the Lattice ECP5 FPGA for the Embedded Vision Development Kit, ideal for Industrial, Medical, and Automotive applications.
    ECP5 / ECP5-5G, CertusPro-NX 
    Image Signal Processing, Lattice mVision, Space 
    Lattice Image Signal Processing Demo
  • Lattice Image Signal Processing Reference Design

    Reference Design

    Lattice Image Signal Processing Reference Design

    Configure an ECP5 FPGA-based ISP solution tailored to your Industrial, Medical, and Automotive application.
    ECP5 / ECP5-5G, CrossLink-NX 
    Image Signal Processing, Lattice mVision 
    Lattice Image Signal Processing Reference Design
  • Human Counting AI Demo

    Demo

    Human Counting AI Demo

    Human upper-body detection and counting demonstration utilizes Lattice’s ECP5 FPGA and a Convolutional Neural Network (CNN) acceleration engine
    ECP5 / ECP5-5G, CrossLink-NX 
    Machine Learning/AI, Object Counting, Object Detection, Lattice sensAI, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, Automotive 
    Human Counting AI Demo
  • Human Face Identification Demonstration

    Demo

    Human Face Identification Demonstration

    Register and identify faces without retraining, eliminating the need for uploading images and lengthy retraining using a GPU.
    ECP5 / ECP5-5G, CertusPro-NX, CrossLink-NX 
    Machine Learning/AI, Object Detection, Object Identification, Lattice sensAI, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, Camera 
    Human Face Identification Demonstration
  • Human Presence Detection AI Demo

    Demo

    Human Presence Detection AI Demo

    Uses an artificial intelligence (AI) algorithm to detect human presence with either the powerful ECP5 FPGA, or small, low-power iCE40 UltraPlus FPGA.
    iCE40 UltraPlus, ECP5 / ECP5-5G 
    Machine Learning/AI, Object Detection, Lattice sensAI, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, UAVs 
    Human Presence Detection AI Demo
  • Package Detection AI Demo

    Demo

    Package Detection AI Demo

    Uses Convolutional Neural Network (CNN) Accelerator IP on the ECP5 FPGA to detect packages. Output is shown via HDMI with a bounding box drawn around packages.
    ECP5 / ECP5-5G 
    Machine Learning/AI, Object Detection, Lattice sensAI 
    Package Detection AI Demo
  • Speed Sign Detection AI Demo

    Demo

    Speed Sign Detection AI Demo

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect speed limit signs and determine the indicated speed.
    ECP5 / ECP5-5G 
    Machine Learning/AI, Object Detection, Object Identification, Lattice sensAI, UAVs 
    Speed Sign Detection AI Demo
  • Vehicle Classification AI Demo

    Demo

    Vehicle Classification AI Demo

    Classifies vehicle types using a Convolutional Neural Network (CNN) Accelerator IP on the ECP5 FPGA. HDMI output uses color-coded bounding boxes.
    ECP5 / ECP5-5G 
    Machine Learning/AI, Object Detection, Object Identification, Lattice sensAI 
    Vehicle Classification AI Demo
  • Bitec DisplayPort IP Core

    IP Core

    Bitec DisplayPort IP Core

    Lattice has partnered with Bitec to bring the DisplayPort 1.4a compliant IP Core (with eDP 1.4 support) to the ECP5 FPGA. Supports resolutions of up to 1080p60
    ECP5 / ECP5-5G, CertusPro-NX 
    DisplayPort, Video Tx/Rx, Lattice mVision 
    Bitec DisplayPort IP Core
  • DisplayPort Receive Demo

    Demo

    DisplayPort Receive Demo

    Uses Bitec's DisplayPort IP core on the ECP5 FPGA in Lattice's Embedded Vision Development Kit. Compliant with DisplayPort 1.4a (including eDP 1.4 support).
    ECP5 / ECP5-5G 
    Video Tx/Rx, DisplayPort, Lattice mVision 
    DisplayPort Receive Demo
  • DisplayPort Transmit Demo

    Demo

    DisplayPort Transmit Demo

    Uses Bitec's DisplayPort IP core on the ECP5 FPGA in Lattice's Embedded Vision Development Kit. Compliant with DisplayPort 1.4a (including eDP 1.4 support).
    ECP5 / ECP5-5G 
    Video Tx/Rx, DisplayPort, Lattice mVision 
    DisplayPort Transmit Demo
  • Tri-Speed Ethernet MAC IP Core

    IP Core

    Tri-Speed Ethernet MAC IP Core

    The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor
    ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, LatticeSC/M, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E 
    Connectivity IP Suite, Data Communication, Ethernet, Ethernet IP Suite, Value IP Suite, Defense, Automotive 
    Tri-Speed Ethernet MAC IP Core
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