Software Defined Radio

Low Power Solutions for Next Generation Communications Systems

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Software Defined Radios (SDR) provide a flexible and programmable communication platform by combining the RF front-end to a digital signal processor. Lattice FPGAs provide a high level of programmability, reconfigurability and control that results in optimized system performance with break-through reduction in system power and size. Lattice FPGAs provide a seamless interface to industry leading RF components to lower development risk and time-to-market. Lattice FPGA resources are optimized with signal processing and memory blocks that are required to implement many waveform types, wide operating frequency bands and wide operating temperature range without the need for cooling.

Lattice’s offers DSP and interface IP, tools and reference designs to enable a plethora of possible solutions and architectures. To accelerate time to market, developers can start with PC based plug-in cards equipped with Lattice FPGAs to capture and manipulate waveforms or to optimize the employed algorithms. Within the FPGA, high bandwidth interfaces offer the ability to transfer blocks of data with low latency using direct memory access from RF sub-system to memory, processing and higher layer system CPU.

Features

  • Up to 1800 DSP blocks and 1000 memory blocks for high performance signal processing
  • Support for high speed Interfaces such as JESD204BC
  • Low Power architectures eliminates thermal challenges
  • Small Form factor packages simplify integration of advanced radio functions

Software Defined Radio

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Block Diagram

Software Defined Radio Block DiagramExpand Image

Low Power Programmable Radio Solution

  • Hardware and software platform to implement key signal processing features
  • Complete and robust radio solution in a small form factor
  • Open source stack with support for GNU radio

Example Applications

RF Sensing & Processing SolutionExpand Image

RF Sensing and Processing Solution

  • Support for JESD204B/C and high speed LVDS connectivity to RF
  • Interoperable with wide variety of common RF front-ends
  • Up to 25Gbps per lane of robust data transfer over backplane and connectors
  • Support for direct Streaming interface from memory over Ethernet
Control Plane Security and Hardware ManagementExpand Image

Control Plane Security and Hardware Management

  • Bridge CPU via PCIe to multiple control plane peripherals (I2C, UART, GPIO), board management functions, and 10GE control plane traffic
  • Security functions (e.g., encryption, authentication) implemented in FPGA helps secure control plane traffic
  • 10G SERDES supporting PCIe Gen 3 x4 (in hard IP) and 10 Gigabit Ethernet (with 10GBASE-R PCS in hard IP)
  • High system reliability and up-time due to 100x lower Soft Error Rate (SER) from FD-SOI technology
  • Fast FPGA configuration supports board management needs and PCIe boot-time requirements

Reference Design

5G Small Cell PCIe to JESD204B Bridge Reference Design

Reference Design

5G Small Cell PCIe to JESD204B Bridge Reference Design

5G Mid-Power Integrated Small Cell, reference platform is a comprehensive development board tailored for 5G baseband processors and transceiver frontends.
CertusPro-NX 
Lattice ORAN, PCIe, JESD204B, 5G, SDR 
5G Small Cell PCIe to JESD204B Bridge Reference Design
Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design

Reference Design

Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design

Lattice ORAN 1.1 RD shows how to provide ultra-reliable time synchronization & phase alignment for delivering timing accuracy in 5G ORAN networks.
CertusPro-NX 
Lattice ORAN, PCIe, SFP, SERDES, FMC, IEEE1588, SDR 
Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design
Redundant Power Supply Management

Reference Design

Redundant Power Supply Management

Uses a Lattice Power Manager II device to achieve Redundant Power Supply Management using the power supply OR’ing technique
Power Manager II 
Mixed-Signal, Power Management, Guidance Systems, Defense, SDR 
Redundant Power Supply Management
JESD204 ADC Reference Design

Reference Design

JESD204 ADC Reference Design

Provides designers an ideal platform for a low cost, low power and small footprint solution for FPGA based serial data acquisition and processing
LatticeECP2/M 
ADC/DAC, DSP, SDR 
JESD204 ADC Reference Design

Demo

MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

Demo

MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.
MachXO5-NX 
L-ASC10, RISC-V, Defense, SDR 
MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration
Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Platform Manager 2 & L-ASC10, MachXO3 
Mixed-Signal, Power Management, TOR Switch, Guidance Systems, 5G, Defense, SDR 
Power Sequencing with Fault Logging Demo
Digital Front End (DFE) Demo

Demo

Digital Front End (DFE) Demo

Lattice DFE (Digital Front End) demonstration utilizing of CPRI (Common Public Radio Interface), DUC (Digital Up Converter) and CFR (Crest Factor Reduction).
LatticeECP3 
CFR, CPRI, DUC, Ethernet, SDR 
Digital Front End (DFE) Demo

IP Cores

FFT Compiler IP Core

IP Core

FFT Compiler IP Core

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, Certus-N2 
Data Communication, DSP, Guidance Systems, Automotive, DSP Bundle, SDR 
FFT Compiler IP Core
FIR Filter Generator IP Core

IP Core

FIR Filter Generator IP Core

This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
ECP5 / ECP5-5G, LatticeECP3, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X, Certus-N2 
DSP, Guidance Systems, Automotive, DSP Bundle, SDR 
FIR Filter Generator IP Core
​​JESD204B IP Core​

IP Core

​​JESD204B IP Core​

​​The Lattice JESD204B IP Core is a high-speed serial interface used between data converters, and the FPGA device to replace traditional interfaces.​
ECP5 / ECP5-5G, LatticeECP3, CertusPro-NX, Avant-G, Avant-X 
ADC/DAC, DSP, SDR 
​​JESD204B IP Core​
10Gb Ethernet MAC+PHY IP Core

IP Core

10Gb Ethernet MAC+PHY IP Core

The Lattice 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
Avant-G, Avant-X, CertusPro-NX 
Ethernet, PCS, XGMII, AXI4, Ethernet Bundle, SDR 
10Gb Ethernet MAC+PHY IP Core
25Gb Ethernet MAC+PHY IP Core

IP Core

25Gb Ethernet MAC+PHY IP Core

The Lattice Semiconductor 25G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
Avant-X 
Ethernet, Lattice Avant, IEEE 802.3, Ethernet Bundle, SDR 
25Gb Ethernet MAC+PHY IP Core
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Development Kits & Boards

Avant-E Evaluation Board

Board

Avant-E Evaluation Board

The Avant-E Evaluation Board has the ability to expand the usability of the Avant-E FPGA with FMC HPC, PMOD, and Raspberry PI connectors.
Avant-E 
Lattice Avant, SPI Flash, LPDDR4, SERDES, GPIO, PMOD, FMC, Industrial Networking, SDR, Defense, Lattice Automate 
Avant-E Evaluation Board
Avant-X Versa Board

Board

Avant-X Versa Board

Avant-X Versa Board support devices that offers a modernized feature set for accelerated system design and fastest soft error detect (SED).
Avant-X 
Lattice Avant, SPI Flash, DDR5, LPDDR4, SERDES, GPIO, PMOD, FMC, Industrial Networking, SDR, Defense 
Avant-X Versa Board
Lattice ORAN Timing and Synchronization Kit

Board

Lattice ORAN Timing and Synchronization Kit

ORAN Sync Board has 2x 10GE & 2x 1GE ports, SMA & FMC connectors for testing, demos, development, GNSS & on-board timing sources, ToD, & PPS RJ48 connectors
CertusPro-NX 
5G, Lattice ORAN, FMC, SMA, IEEE1588, SDR 
Lattice ORAN Timing and Synchronization Kit
LimeSDR Mini Development Board by Lime Microsystems

Board

LimeSDR Mini Development Board by Lime Microsystems

LimeSDR Mini Dev Board is a low cost, open source and apps-enabled SDR platform that can be used to support any type of wireless communication standard.
ECP5 / ECP5-5G 
Community Sourced, RF Transceiver, FTDI, GPIO, JTAG, Defense, SDR 
LimeSDR Mini Development Board by Lime Microsystems
CertusPro-NX Evaluation Board

Board

CertusPro-NX Evaluation Board

CertusPro-NX Evaluation Board, a FPGA-based rapid prototyping and testing of specific designs with the features of CertusPro-NX FPGA family.
CertusPro-NX 
Breakout, SMA, SPI Flash, Raspberry Pi, FMC, SERDES, PMOD, Automotive, SDR 
CertusPro-NX Evaluation Board

Documentation

Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Comparative Study on Low Power FPGA Solutions
WP0037 1.0 4/23/2024 PDF 2 MB
5G OFDM Modulation with Lattice iFFT and FIR IPs Use Case
WP0042 3/25/2025 PDF 3.8 MB
Rapid Prototype Work Flow with HDL Coder - 5G OFDM and Single Tone Modulation Use Case
WP0039 1.0 8/8/2024 PDF 1.8 MB

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