DDR and I/O Design Resources

The following information is a summary of available resources to help you with all aspects of implementing DDR (1/2/3/etc.) and I/O design for Lattice programmable products.


The following documents are available on the Lattice website.

I/O Design
Product Family Title
CrossLink FPGA-TN-02016 CrossLink sysI/O Usage Guide
CrossLink FPGA-TN-02013 CrossLink Hardware Checklist
MachXO3 TN1282 MachXO3 sysIO Usage Guide
MachXO3 TN1281 MachXO3 Implementing High-Speed Interfaces with MachXO3 Devices
MachXO2 TN1202 MachXO2 sysIO Usage Guide
MachXO2 TN1208 MachXO2 Hardware Checklist
LatticeXP2 TN1136 LatticeXP2 sysIO Usage Guide
LatticeXP2 TN1143 LatticeXP2 Hardware Checklist Technical Note
ECP5 TN1265 ECP5 and ECP5-5G High-Speed I/O Interface
ECP5 TN1262 ECP5 and ECP5-5G sysIO Usage Guide
LatticeECP3 TN1189 LatticeECP3 Hardware Checklist
LatticeECP3 TN1177 LatticeECP3 sysIO Usage Guide
LatticeECP2/M TN1102 LatticeECP2/M sysIO Usage Guide
LatticeECP2/M TN1159 LatticeECP2/M Pin Assignment Recommendations
LatticeECP2/M TN1162 LatticeECP2/M Hardware Checklist Technical Note
All TN1033 High-Speed PCB Design Considerations
All TN1068 Power Decoupling and Bypass Filtering for Programmable Devices
All TN1074 PCB Layout Recommendations for BGA Packages
DDR Design
Product Family Title
CrossLink FPGA-TN-02012 CrossLink High-Speed I/O MIPI D-PHY and DDR Interfaces
MachXO2 TN1203 Implementing High-Speed Interfaces with MachXO2 Devices
LatticeXP2 TN1138 LatticeXP2 DDR and High-Speed I/O Interface
LatticeECP3 TN1180 LatticeECP3 DDR and High-Speed I/O Interface
LatticeECP2/M TN1105 LatticeECP2/M DDR and High-Speed I/O Interface


The following FAQs are some of the more popular items pertaining to DDR3 and I/O Design.

On the Lattice Website

Visit the following pages to learn more about various Lattice topics, products, demos, features and more.

Lattice DDR Memory Controller IP Cores

Lattice Evaluation Boards and Development Kits with DDR memory interfaces

Outside Lattice

Here are some links & resources you might find useful, relating to DDR & I/O design.

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