The high-speed AES256-CTR from Xiphera implements the Advanced Encryption Standard (AES) in Counter Mode (CTR). The Counter mode of operation effectively turns a block cipher into a stream cipher, and provides a number of advantages from an implementation point of view. These include the ability to use the same key expansion functionality and datapath for both encryption and decryption, and the possibility to parallelize the FPGA-based implementation by unrolling and pipelining.
Performance: Despite its moderate size, the high-speed AES-CTR IP core achieves a throughput in the Gbps range, for example 16.50+ Gbps in Lattice ECP5.
Standard Compliance: The IP core is fully compliant with both the Advanced Encryption Algorithm (AES) standard and the Counter Mode (CTR) standard.