Convolutional Neural Network (CNN) Compact Accelerator

Implement Machine Learning Inferencing in mWs

Related Products

Related Applications


iCE40 UltraPlus Mobile Development Platform

Take advantage of the FPGA’s parallel processing capability to implement compact CNNs including binarized versions known as BNNs. This IP enables you to implement CNNs in the Lattice iCE40 UltraPlus FPGAs that have power consumption in the mW range.

This IP uses on-chip DSP resources of the iCE40 UltraPlus devices to implement CNNs. Eleven Embedded Block Ram (EBR) are used as working memory by the acceleration engine. Users can choose to use EBR or the larger Single Port Memory (SPRAM) blocks to store the weights and instructions used by the engine.

This IP is paired with the Lattice Neural Network Compiler tool. The compiler takes networks developed in common NN training tools, and allows compilation into instructions that can be run by the Accelerator IP.

  • Implement deep learning with mW power consumption
  • Implement CNNs including BNNs in iCE40 UltraPlus using on-chip DSP and memory blocks
  • Compatible with common network structures such as Mobilenet and VGG
  • Network weight and operation sequence stored in either EBR or SPRAM blocks
Lattice sensAI

Jump to

Block Diagram

BNN Implementations

Binarized Neural Network (BNN) Accelerator IP Block Diagram

CNN Implementations

CNN Block Diagram

Performance and Size

iCE40 UltraPlus Performance and Resource Utilization in BNN Mode1
Memory Type BNN Blob Type Registers LUTs EBR SRAM clk Fmax2 (MHz)
EBRAM +1/0 1822 2419 27 0 41.762
DUAL_SPRAM +1/0 1803 2447 11 2 31.565
SINGLE_SPRAM +1/0 1802 2430 11 1 41.103
SINGLE_SPRAM +1/-1 1992 2706 11 1 40.748

1. Generated using Lattice Radiant Software 1.0.0.350.0 with Lattice Synthesis Engine targeting to iCE40 UP5K-SG48I. Performance may vary when using a different software version or targeting a different device density or speed grade.
2. Fmax is generated when the FPGA design only contains Compact CNN Accelerator IP Core, these values may be reduced when user logic is added to the FPGA design.

iCE40 UltraPlus Performance and Resource Utilization in CNN Mode1
Memory Type Scratch Pad3 Registers LUTs EBR SRAM clk Fmax2 (MHz)
EBRAM 1K 1725 2816 23 0 28.164
DUAL_SPRAM 1K 1706 2867 7 2 27.672
SINGLE_SPRAM 1K 1705 2841 7 1 26.782
SINGLE_SPRAM 4K 2052 3989 19 1 25.950

1. Generated using Lattice Radiant Software 1.0.0.350.0 with Lattice Synthesis Engine targeting to iCE40 UP5K-SG48I. Performance may vary when using a different software version or targeting a different device density or speed grade.
2. Fmax is generated when the FPGA design only contains Compact CNN Accelerator IP Core, these values may be reduced when user logic is added to the FPGA design.
3. The K value in Scratch Pad is equivalent to kilobyte. For example, 1K is equal to 1 kB of scratch pad memory.

Ordering Information

Family OPN Description
iCE40 UltraPlus CNN-CPACCEL-UP-U Single Design License
iCE40 UltraPlus CNN-CPACCEL-UP-UT Multi-Site Design License

To request a 30-day evaluation license for the Compact CNN Accelerator, click here.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Compant CNN Accelerator IP User Guide
FPGA-IPUG-02038 1.7 12/16/2020 PDF 1.2 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW