I2C Slave IP Core

I2C Bus Interface

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I2C (Inter-Integrated Circuit) bus is a simple, low-bandwidth, short-distance protocol. It is often seen in systems with peripheral devices that are accessed intermittently. It is commonly used in short-distance systems, where the number of traces on the board should be minimized. The device that initiates the transmission on the I2C bus is commonly known as the Master, while the device being addressed is called the Slave.

Lattice Semiconductor general-purpose I2C Slave IP Core provides device addressing, read/write operation and an acknowledgement mechanism. The programmable nature of FPGA provides users with the flexibility of configuring the I2C Slave device to any legal Slave address, thus, avoiding a potential Slave address collision on an I2C bus with multiple Slave devices.

Features

  • Supports 7-bit and 10-bit Addressing Mode, supporting the bus speeds: Standard-mode (Sm) – up to 100 kbit/s, Fast-mode (Fm) – up to 400 kbit/s and Fast-mode Plus (Fm+) – up to 1 Mbit/s
  • Integrated Pull-up and Glitch filter
  • Polling and Out-of-band Interrupt Modes
  • Supports Clock stretching
  • Configurable ACK/NACK response on address and data phases

Block Diagram

I2C Slave IP Core Block DiagramExpand Image

Performance and Size

Nexus Family
LFMXO5-25-9BBG400I
Configuration Clk Fmax (MHz)* Slice Registers LUTs EBRs
Default 168 319 397 0
APB Mode Enable: false,
Others = Default		 200 304 370 0
Implementation of FIFO = EBR,
Others = Default		 157 303 364 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 168 319 385 0
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 256,
RX FIFO Almost Full Flag: 256,
Others = Default		 167 349 1088 0

Note: Fmax is generated when the FPGA design only contains I2C Slave IP Core, and the target frequency is 50MHz. These values may be reduced when user logic is added to the FPGA design.

LFMXO5-25-7BBG400I
Configuration Clk Fmax (MHz)* Slice Registers LUTs EBRs
Default 101 319 385 0
APB Mode Enable: false,
Others = Default		 120 304 370 0
Implementation of FIFO = EBR,
Others = Default		 103 303 365 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 94 319 385 0
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 256,
RX FIFO Almost Full Flag: 256,
Others = Default		 101 349 1089 0

Note: Fmax is generated when the FPGA design only contains I2C Slave IP Core, and the target frequency is 50MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I2C Slave IP Core - Lattice Radiant Software
FPGA-IPUG-02072 1.4 5/31/2022 PDF 703.8 KB

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