Scatter-Gather DMA Controller IP Core

Implements a Configurable, AXI Lite-compliant DMA Controller with Scatter-Gather Capability

The Scatter Gather Direct Memory Access Controller (SDMAC) IP core provides access to the main memory independent of the processor. It offloads processor intervention. The processor initiates transfer to SGDMAC and receives an interrupt on completion of the transfer by the DMA Engine.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Independent MM2S and S2MM data buffer
    • MM2S: AXI-MM to AXI-Stream
    • S2MM: AXI-Stream to AXI-MM
  • AXI4 Protocol compliant
    • MM2S/S2MM AXI4-MM Address width support of 32 or 64 bits.
    • MM2S/S2MM AXI4-MM Data width support of 32, 64 or 128 bits.
    • MM2S/S2MM AXI4-Steam Data width support of 8, 16, 32, 64 or 128 bits.
    • Buffer Descriptor AXI4-MM Address and Data width support of 32 bits.
    • AXI4-Lite Address and Data width support of 32 bits.
  • Max transfer size per descriptor support of 2^16 Bytes.
  • Any-to-any AXI-MM and AXI-S Data Width streaming.
  • Configurable MM2S/S2MM local FIFO Depth support of 512, 1024, 2048 or 4096.

Jump to

Block Diagram

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G DMA-SG-AVG-UT DMA-SG-AVG-US
Avant-X DMA-SG-AVX-UT DMA-SG-AVX-US
Avant-E DMA-SG-AVE-UT DMA-SG-AVE-US
CertusPro-NX DMA-SG-CPNX-UT DMA-SG-CPNX-US
ECP5 DMA-SG-E5-UT DMA-SG-E5-US
LatticeECP3 DMA-SG-E3-UT1 DMA-SG-E3-US
LatticeECP2 DMA-SG-P2-UT1 -
LatticeECP2M DMA-SG-PM-UT1 -
LatticeSC/M DMA-SG-SC-UT1 -
LatticeXP2 DMA-SG-X2-UT1 -

IP Version: 2.5.

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Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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Scatter-Gather Direct Memory Access Controller IP Core User's Guide
IPUG67 1.8 3/1/2015 PDF 3.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB

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