DDR3 SDRAM Controller

General Purpose DDR3 Memory Interface Controller

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The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices/modules compliant with JESD79-3, DDR3 SDRAM Standard, and provides a generic command interface to user applications. The DDR3 SDRAM is the next-generation DDR SDRAM memory technology which features faster speed, mitigated SSO, and reduced routing due to “fly-by” routing signals to SDRAM instead of low skew tree distribution. This core reduces the effort required to integrate the DDR3 memory controller with the remainder of the application and minimizes the need to directly deal with the DDR3 memory interface.

DDR3 SDRAM Controller IP Core Pinout Generation Utility

The DDR3 Pinout Generation Utility is a GUI tool capable of generating the pinout and preference files that contain information for a design that uses the DDR3 SDRAM Controller IP core. More information about this utility, including downloads and documentation is available here.

Features

  • Interfaces to Industry Standard DDR3 SDRAM components and modules compliant with JESD79-3, DDR3 SDRAM Standard
  • Interfaces to DDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices
  • Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits
  • Supports x4, x8, and x16 device configurations
  • Support for unbuffered DDR3 DIMM and DDR3 RDIMM module

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Block Diagram

DDR SDRAM Controller

Performance and Size

ECP51
Parameters SLICEs LUTs Registers I/O2 fMAX (MHz)3
Data Bus Width: 8 (x8) 1800 2600 1700 42
 400 MHz (800 Mbps)
Data Bus Width: 16 (x8) 1900 2650 1900 53
 400 MHz (800 Mbps)
Data Bus Width: 24 (x8) 2000 2850 2050 64
 400 MHz (800 Mbps)
Data Bus Width: 32 (x8) 2100 2950 2250 75
 400 MHz (800 Mbps)
Data Bus Width: 40 (x8) 2200 3000 2450 86
 400 MHz (800 Mbps)
Data Bus Width: 48 (x8) 2450 3200 2650 97
 400 MHz (800 Mbps)
Data Bus Width: 56 (x8) 2600 3250 2850 108
 400 MHz (800 Mbps)
Data Bus Width: 64 (x8) 3450 3450 3100 119
 400 MHz (800 Mbps)
Data Bus Width: 72 (x8) 3500 3500 3300 130
 333 MHz (666 Mbps)

1. Performance and utilization data are generated targeting an LFE5U/LFE5UM-85F-8MG756 device using Lattice Diamond 3.2 design software with an LFE5U/LFE5UM control pack. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.
2. Numbers shown in the I/O column represent the number of primary I/Os at the DDR3 memory interface. User interface (local side) I/Os are not included.
3. The DDR3 IP core can operate at 400 MHz (800 DDR3) in the fastest speed-grade (-8) when the data width is 56 bits or less and one chip select is used.

LatticeECP31, 2,3
Parameters SLICEs LUTs Registers I/O fMAX (MHz)
Data Bus Width: 8 (x8) 1741 2519 1764 42 400 MHz (800 Mbps)
Data Bus Width: 16 (x8) 1947 2661 2129
 53 400 MHz (800 Mbps)
Data Bus Width: 24 (x8) 2157
 2820 2467 64 400 MHz (800 Mbps)
Data Bus Width: 32 (x8) 2337 2934 2803 75 400 MHz (800 Mbps)
Data Bus Width: 40 (x8) 2266 2890 2685 86 400 MHz (800 Mbps)
Data Bus Width: 48 (x8) 2401 2968 2886 97 400 MHz (800 Mbps)
Data Bus Width: 56 (x8) 2532 3080
 3112
 108 400 MHz (800 Mbps)
Data Bus Width: 64 (x8) 2662 3212
 3320
 119 400 MHz (800 Mbps)
Data Bus Width: 72 (x8) 2795 3348 3469 130 333 MHz (666 Mbps)

1. Performance and utilization data are generated targeting an LFE3-150EA-8FN1156C device using Lattice Diamond 1.4 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.
2. EA silicon support only.
3. The DDR3 IP core can operate at 400 MHz (800 DDR3) in the fastest speed-grade (-8, -8L, or -9) when the data width is 64 bits or less and one chip select is used.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
CertusPro-NX DDR3-P-CPNX-UT DDR3-P-CPNX-US
Certus-NX DDR3-P-CTNX-UT DDR3-P-CTNX-US
CrossLink-NX DDR3-P-CNX-UT DDR3-P-CNX-US
ECP5 DDR3-E5-UT DDR3-E5-US
LatticeECP3 (EA) DDR3-P-E3-UT1 DDR3-P-E3-US

IP Version: 1.4.

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeECP3 DDR3 Demo for the LatticeECP3 I/O Protocol Board User's Guide
UG38 01.4 6/8/2012 PDF 2.7 MB
DDR3 SDRAM Controller IP Core - Lattice Radiant Software
FPGA-IPUG-02086 1.7 3/11/2024 PDF 1.5 MB
DDR3 SDRAM Controller IP Core - Lattice Diamond Software
FPGA-IPUG-02047 2.2 10/11/2020 PDF 3.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Implementing DDR3 Memory Controller (LatticeECP3)
1.0 3/10/2010 PDF 147.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeECP3 DDR3 Demo
1.4 6/8/2012 ZIP 235.3 KB

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