The H.264-ENC1 encoder IP is a high performance HD compression core IP that implements the H.264 (MPEG-4/AVC) video coding standard. This encoder core compresses HD and SD video through the use of advanced algorithms and can be implemented in a low cost FPGA. Our superior quality compression is achieved by using such features as a proprietary high performance motion estimation engine, frequency domain noise filtering, and intelligent macroblock skipping.
Supported resolutions range from 64x64 pixels through 2048x2048, including all standard resolutions such as QCIF, CIF, D1, 720p, 1080p, 2K, etc. The core can also process video at any frame rate. The resulting compressed bit rates can be as low as 64 Kbit/s or as high as 250 Mbits/s, depending on content, resolution and frame rate. This wide bit rates range of and quality make the core suitable in a very broad range of applications including surveillance, medical, and broadcasting.
The H.264-ENC1 core has been designed and optimized specifically for use with Lattice Semiconductor ECP3 and ECP2/M FPGAs. A block diagram of a full featured core is given below.
A Video Compression Evaluation Platform based on a Lattice Semiconductor ECP3 FPGA and referred to as LT-125 is available directly from Enciris Technologies.