Baseline and Extended JPEG Decoder

Related Products

JPEG decompression IP core supports Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard.

Cast LogoAn area efficient, high performance JPEG decoder core for FPGA with very low processing latency.

JPEG-DX-S Decoder decompresses JPEG images and the video payload for Motion JPEG container formats for images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.

  • Single-frame JPEG images and Motion JPEG payloads with four colour components, with 8- or 12-bit colour samples
  • Multiple interface support like, AXI Streaming pixel compressed stream interfaces, and APB Control/Status interface
  • High performance Synthesis-time configurable scalable throughput with up to 32 samples per clock cycle
  • Easy to integrate, requires no programming or control from host, with marker syntax errors detection and reporting
  • Optional Block-to-Raster Con-version with AXI or standard memory interface towards the lines buffer

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Block Diagram

Performance and Size

Family Logic Utilization Block RAMs DSP FMAX (MHz)
ECP5U / LAE5U-12F 8,340 Slices
11,843 LUT4s
9 8 70

The utilization for the IP is available based on current implementation for the devices shown in the table above. The IP can also be made available for other Lattice devices. For utilization on devices other than shown above, please contact CAST Sales Team for more information.

Ordering Information

This IP core is supported and sold by CAST, contact CAST at or visit their website at for more information.


Information Resources
CAST’s JPEG-DX-S Core Product Brief
1.0 5/29/2018 PDF 297.8 KB

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