Bitec DisplayPort IP Core

DisplayPort and Embedded DisplayPort IPs for Low-power FPGAs

Lattice has partnered with Bitec to bring the DisplayPort 1.4a compliant IP Core (with eDP 1.4 support) to low-power, production-priced ECP5 devices.

With feature rich parametrization, the IP core is optimized for system designers to use for a variety of applications like consumer, industrial and automotive.

ECP5 SERDES is used in the IP core for up to 4-lanes support with 2.7 Gbps per lane data rates to support resolutions of up to 1080p60.

  • DisplayPort 1.4a compatible (includes eDP 1.4) with 1, 2 and 4 lanes for both transmit and receiver
  • Multiple bit color-depth support in RGB or YCbCr Colorimetric formats
  • Embedded DisplayPort (eDP) features supported
  • 8-Channel audio and optional HDCP support

Ordering Information

  • This IP core is supported and sold by BITEC.

Jump to

Block Diagram

  • DisplayPort 1.4 specification with 1, 2 & 4 lane support
  • Supports link rate of 1.62 Gbps or 2.7 Gbps
  • Dual and quad symbol modes support with Single, Dual and Quad pixel modes
  • 4-, 8-, 10-, 12- and 16-bit color support with RGB or YCbCr formats

Design Resources

Bitec DisplayPort IP Core

IP Core

Bitec DisplayPort IP Core

Lattice has partnered with Bitec to bring the DisplayPort 1.4a compliant IP Core (with eDP 1.4 support) to the ECP5 FPGA. Supports resolutions of up to 1080p60
Bitec DisplayPort IP Core
DisplayPort VIP Input Board

Board

DisplayPort VIP Input Board

Expands the Lattice VIP board ecosystem to support DisplayPort 1.4a (DP) video input - up to 4 lanes at 1.62 or 2.7 Gbps.
DisplayPort VIP Input Board
DisplayPort VIP Output Board

Board

DisplayPort VIP Output Board

Expands the Lattice VIP board ecosystem to support DisplayPort 1.4a (DP) video output - up to 4 lanes at 1.62 or 2.7 Gbps.
DisplayPort VIP Output Board

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Bitec DisplayPort Lattice Integration Manual
Note: for latest documents please contact Bitec directly.
1.0 3/28/2018 PDF 481 KB
DisplayPort VIP Output Board Evaluation Board User Guide
FPGA-EB-02015 1.0 4/21/2018 PDF 653 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Bitec DisplayPort IP Product Brief
2.0 6/25/2021 PDF 174.9 KB

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