Human Face Detection

Lattice sensAI Demo

Detect the presence of a human face in under a 1 mW – This demo uses artificial intelligence (AI) to implement a human detection algorithm. FPGAs have parallel data processing ability, making them more power efficient at such tasks compared to a microprocessor.

Always-on, local intelligence improves security – Bringing AI to the network edge is challenging, but it also offers tremendous opportunity. Designing AI into an iCE40 UltraPlus FPGA instead of cloud-based resources can dramatically cut power consumption while accelerating response time. At the same time, keeping processing local improves security. Additionally, designers gain always-on intelligence, even when the network is turned off to save power.

Multi-engine BNN in a 2.15 mm x 2.55 mm FPGA – The Lattice inference engine with BNN architecture is able to fit into two package options in our iCE40 UltraPlus FPGA. A 30-ball CSP package with 0.4 mm ball pitch created the smallest neural network within an FPGA, 2.15 mm x 2.55 mm. A 48-pin QFN package with 0.5 mm pin pitch enables lower cost PCB designs, 7.0 mm x 7.0 mm.

Features

  • Accelerated, low-power face detection at network edge using neural network model
  • Configuration files provided for rapid implementation on iCE40 UltraPlus Mobile Development Platform
  • Binary weights and activation reduce overall power consumption, while maintaining high accuracy
  • With integrated 128K bytes of memory, weights/activations can be stored directly inside of iCE40 UltraPlus FPGA
  • Can be optimized between power and response time depending on system needs
  • The same technique can be used to detect other objects such as dog, cat, car, or ship
Lattice sensAI

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Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
MDP Based Face Detection Demonstration User Guide
FPGA-UG-02047 1.1 9/25/2018 PDF 1001.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
MDP Based Face Detection Demonstration Bitstreams
1.1 9/25/2018 ZIP 2 MB


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